Embedded Semiconductor Circuit Board Thermal Stress Management

The patent applies asymmetry by processing circuit build-up only on one surface of the core circuit board rather than both surfaces. The method forms dielectric layers and circuit layers alternately stacked on the surface of the core circuit board, with conductive structures formed in the dielectric layers, creating an asymmetrical build-up structure that simplifies manufacturing while accommodating different circuit layout requirements for upper and lower surfaces.

The patent segments the circuit board into a core circuit board and separate build-up layers. The core circuit board serves as the base structure, while dielectric layers and circuit layers are segmented and stacked alternately on one surface. This segmentation allows independent optimization of the core board and the build-up structure, reducing manufacturing complexity while maintaining stability.

The patent applies local quality by concentrating high-density circuit build-up only on the surface requiring high integration, while the opposite surface maintains lower circuit density. The dielectric layers and circuit layers are alternately stacked and configured according to local circuit density requirements, allowing high integration where needed while maintaining thermal stress balance across the entire board structure.

The patent uses composite materials by alternating dielectric layers with different coefficients of thermal expansion and circuit layers. This composite structure is designed to balance thermal stresses - the dielectric layers provide mechanical support and thermal management, while the circuit layers provide electrical functionality. The alternating stack compensates for thermal expansion differences, preventing warpage and delamination even with asymmetric circuit density.

The patent applies nesting by embedding semiconductor elements within the core circuit board structure. Through holes are formed in the core circuit board, and semiconductor elements are received and secured inside these through holes. The dielectric layers and encapsulation structures surround and protect the embedded elements, creating a nested configuration that achieves miniaturization while providing mechanical protection and thermal stress isolation.

The patent provides beforehand cushioning by forming encapsulation layers around the embedded semiconductor elements before final assembly. The encapsulation layers, formed from the alternating dielectric and circuit layers, act as protective cushions that absorb and distribute thermal stresses. This pre-formed protection prevents direct transmission of thermal stress to the sensitive semiconductor elements during temperature changes in fabrication and operation.