Embedded Semiconductor Logic Device with Copper Pillar Interconnects
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Solution Overview
Problem
High-end semiconductor logic chips face challenges in miniaturization due to limitations in flip chip solder bump technology, which restricts die size reduction and increases costs and yield losses, especially when transitioning to smaller feature nodes, and embedded chip packaging yields are low for complex devices with high I/O counts.
Innovation Solution
The solution involves a semiconductor logic device with signal I/O pads arranged at a smaller pitch and power/ground I/O pads at a larger pitch, integrated with an interconnect layer that includes insulating and conductive layers with vias, allowing for direct metallurgical interconnections without solder, enabling a reconfiguration layer with discrete terminal pads for improved electrical performance and packaging yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If flip chip solder bump technology is used to mount high pin count semiconductor logic devices, then the device can be connected to interconnect structures, but the minimum solderable pitch (120-160 microns) prevents die size reduction and increases fabrication costs
Solution Approach 1:
The patent replaces the mechanical solder bump attachment system with a direct metallurgical interconnection system. Copper pillars are formed directly on the I/O pads through electroplating, eliminating the need for solder bumps and enabling pitch reductions below the 120-160 micron solderable minimum. This substitution allows die shrinkage while maintaining reliable electrical connections.
Solution Approach 2:
The patent changes the interconnection parameter from solder-based mechanical attachment to direct copper metallurgical bonding. This parameter change enables smaller pitch values (below 120 microns) and allows the die size to be reduced without compromising connection reliability, directly addressing the manufacturing precision constraint.
2Reliability
If the number of power and ground I/O pads is increased to meet high current requirements, then power and ground conductivity is improved, but the chip size increases and wafer level chip yields decrease
Solution Approach 1:
The patent applies local quality by creating larger copper pillars specifically at power and ground I/O pad locations. These enlarged copper pillars provide enhanced current carrying capacity and lower resistance where high current flows, while signal I/O pads use standard-sized copper pillars. This localized enhancement maintains power/ground conductivity without requiring a uniform increase in chip size.
Solution Approach 2:
The patent introduces asymmetry in the copper pillar dimensions based on functional requirements. Power and ground I/O pads receive larger copper pillars (e.g., 150-200 microns diameter) compared to signal I/O pads (e.g., 50-100 microns diameter). This asymmetric design optimizes current distribution and reduces the total number of pads needed, thereby reducing chip size while maintaining conductivity requirements.
3Productivity
If semiconductor feature sizes are reduced to increase gates per unit area, then functionality per chip is improved, but the minimum pitch for solder bumped flip chip devices prevents die shrinkage
Solution Approach 1:
The patent replaces the solder bump mechanical attachment system with direct copper pillar metallurgical interconnection. This substitution removes the 120-160 micron minimum pitch constraint that prevents die shrinkage, allowing the die size to be reduced proportionally with feature size scaling while maintaining connection reliability.
Solution Approach 2:
The patent moves the interconnection approach to a different dimensional regime by using direct copper pillar bonding instead of solder bumps. This enables pitch values below the traditional solderable minimum, allowing die size to shrink at the same rate as feature sizes, thereby maintaining gates per unit area productivity.
4Ease of manufacture
If embedded chip packaging is used for complex devices with high I/O counts, then packaging is achieved, but yields are low due to interconnect structure complexity
Solution Approach 1:
The patent extracts the complex interconnect structure from the packaging process and integrates it directly into the semiconductor device fabrication. Copper pillars are formed on the I/O pads during device manufacturing, and the interconnect layers are built up concurrently with device processing. This extraction of the interconnect structure from the packaging stage eliminates yield losses associated with post-embedding interconnect defects.
Solution Approach 2:
The patent performs preliminary action by forming copper pillars and building interconnect layers during the semiconductor device fabrication process itself, before the device is embedded in the package. This preliminary formation of interconnections ensures their reliability is established during device manufacturing when process control is optimal, rather than during subsequent packaging operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a 20-30% die size reduction and lower fabrication costs while maintaining or improving power and ground signal delivery, reducing yield losses, and providing higher electrical performance and interconnect yields compared to traditional methods.
Implementation Method 1
Each of the at least one interconnect layers includes an insulating layer and a conductive layer formed on the insulating layer and extending into a plurality of vias formed therethrough. The conductive layer is electrically coupled to the plurality of signal I/O pads, the plurality of power I/O pads, and the plurality of ground I/O pads.
Data Source
AI summary
An embedded semiconductor package includes a semiconductor logic device comprising a plurality of signal input/output (I/O) pads spaced at a first pitch on an active surface thereof and a plurality of power I/O pads and ground I/O pads spaced on the active surface at a second pitch larger than the first pitch. At least one interconnect layer overlies the semiconductor logic device. Each of the at least one interconnect layers includes an insulating layer and a conductive layer formed on the insulating layer and extending into a plurality of vias formed therethrough. The conductive layer is electrically coupled to the plurality of signal I/O pads and the plurality of power I/O pads and ground I/O pads.