Embedded Semiconductor Package Interconnect Structure
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Solution Overview
Problem
Existing electronics packaging methods result in increased thickness due to the use of multilayer printed circuit boards, which hinders miniaturization and efficiency in semiconductor device packages, necessitating a solution for a thinner, more densely interconnected package.
Innovation Solution
The method involves a functional web assembly with dielectric layers and metalized interconnects on both sides, allowing for embedded die placement and reduced thickness by eliminating the need for a bulky PCB, incorporating die openings, adhesive layers, and additional metal interconnection layers for increased routing and interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a multilayer printed circuit board is used to mount individually packaged semiconductor devices, then the electrical interconnection and mounting capability is provided, but the overall package thickness increases considerably
Solution Approach 1:
The patent extracts and eliminates the multilayer printed circuit board from the package structure. Instead of mounting devices on a PCB, the semiconductor devices are directly embedded into the package substrate, removing the bulky PCB while maintaining electrical interconnection capabilities through direct bonding and wire bonding techniques
Solution Approach 2:
The patent embeds semiconductor devices directly within the package substrate structure. The devices are nested into cavities or recesses formed in the substrate, with multiple layers of devices stacked vertically, creating a compact three-dimensional arrangement that eliminates the need for a separate PCB mounting layer
2Reliability
If individually packaged semiconductor devices are mounted on a PCB, then the devices can be electrically connected, but the package size and thickness increase
Solution Approach 1:
The patent merges the PCB mounting function with the package substrate itself. The substrate is designed to provide both mechanical support and electrical interconnection pathways, combining what were previously separate functions (PCB mounting + package housing) into a single integrated structure
Solution Approach 2:
The patent transitions from a two-dimensional PCB mounting approach to a three-dimensional embedded structure. Devices are arranged in multiple vertical layers within the substrate, utilizing the vertical dimension to increase interconnection density without increasing the package footprint
Data Source
Figure 1
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Figure 6~8
AI summary
An electronics package includes a first dielectric substrate (34) having a first plurality of vias (50) formed through a thickness thereof, a metalized contact layer (48) coupled to a top surface (40) of the first dielectric substrate (34), and a first die (68) positioned within a first die opening (58) formed through the thickness of the first dielectric substrate (34). Metalized interconnects (56) are formed on a bottom surface (54) of the first dielectric substrate (34) and extend through the first plurality of vias (50) to contact the metalized contact layer (48). A second dielectric substrate (64) is coupled to the first dielectric substrate (34) and has a second plurality of vias (82) formed through a thickness thereof. Metalized interconnects (92) extend through the second plurality of vias (82) to contact the first plurality of metalized interconnects (56) and contact pads (49) of the first die (68). A first conductive element electrically (114) couples the first die (68) to the metalized contact layer (48).