Embedded Semiconductor Package with Connection Window
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Solution Overview
Problem
The challenge lies in reducing the thickness of semiconductor packages while maintaining electrical connectivity, as the thickness of the package substrate and bonding wires limits miniaturization, and vertically stacked chips increase package thickness due to the need for epoxy molding compound encapsulation.
Innovation Solution
A semiconductor package design featuring an embedding substrate with a cavity and connection window, where semiconductor chips are embedded with dielectric layers exposing chip connectors, allowing for external connections and reduced package thickness through a hybrid embedded package form.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to electrically connect the semiconductor chip to the package substrate, then electrical connectivity is achieved, but the loop height of bonding wires increases the package thickness
Solution Approach 1:
The patent extracts the bonding wire connection function and replaces it with direct chip-to-substrate mounting. The semiconductor chip is mounted directly on the package substrate with chip connectors contacting connection windows, eliminating the bonding wire loop structure and its associated height, while maintaining electrical connectivity through direct contact paths.
Solution Approach 2:
The patent introduces connection windows as intermediary structures in the package substrate. These connection windows provide direct electrical contact paths between chip connectors and the package substrate, serving as mediators that eliminate the need for bonding wires while maintaining reliable electrical connectivity.
2Area of stationary object
If vertically stacked semiconductor chips are used to reduce package footprint, then miniaturization is achieved, but the package thickness increases due to epoxy molding compound encapsulation
Solution Approach 1:
The patent transitions from vertical stacking (z-dimension) to lateral arrangement (x-y plane) of semiconductor chips. Multiple chips are mounted side-by-side on the package substrate, utilizing horizontal space instead of vertical stacking, thereby reducing package thickness while achieving miniaturization through efficient use of substrate area.
Solution Approach 2:
The patent segments the package design into multiple independent chip mounting regions on the substrate. Instead of stacking chips vertically, the package is divided into separate lateral zones where individual chips can be mounted independently, allowing for reduced thickness while maintaining multiple functional elements.
3Length of stationary object
If package substrate thickness is reduced to minimize package thickness, then miniaturization is achieved, but manufacturing precision and reliability are compromised
Solution Approach 1:
The patent incorporates connection windows directly into the package substrate during substrate fabrication, before chip mounting. This preliminary formation of connection windows ensures precise positioning and dimensional control are built into the substrate structure itself, maintaining manufacturing precision even as overall package thickness is reduced.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the package substrate. The connection windows provide localized precision features for electrical contact, while the overall substrate can be optimized for thinness. This local differentiation allows thickness reduction without compromising the precision required for electrical connectivity.
Data Source
AI summary
Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.