Embedded SiGe Structure Stacking Fault Reduction
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Solution Overview
Problem
High Ge content in embedded SiGe source/drain regions leads to significant stacking faults, deteriorating semiconductor device performance.
Innovation Solution
A method involving the formation of a SiGe seed layer on sidewalls, a first SiGe layer with gradually increasing Ge content from bottom to top, and a second SiGe layer with constant Ge content, along with a cap layer, to reduce Ge content gradients and prevent stacking faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the content of Ge in the embedded SiGe material is increased to apply higher compressive stress to the channel region, then the carrier mobility and device performance are improved, but stacking faults occur substantially on the interface between Si and SiGe
Solution Approach 1:
The SiGe layer is segmented into multiple sub-layers with different Ge contents (first SiGe layer with 5-20 at.% Ge, second SiGe layer with 20-30 at.% Ge, third SiGe layer with 30-40 at.% Ge). This segmentation creates a gradient structure that reduces the abruptness of the interface between Si and SiGe, thereby reducing stacking faults while maintaining high Ge content for carrier mobility enhancement.
Solution Approach 2:
Different regions of the SiGe structure have different Ge contents tailored to their specific functions. The first SiGe layer closer to the Si substrate has lower Ge content to reduce interface stress, while the third SiGe layer farther from the substrate has higher Ge content to provide strong compressive stress to the channel region. This local quality variation optimizes both interface stability and device performance.
2Productivity
If the content of Ge in the embedded SiGe material exceeds 30 at.%, then significant improvement of PMOS performance is achieved, but stacking faults substantially occur on the interface between Si and SiGe
Solution Approach 1:
The SiGe structure is divided into three layers with progressively increasing Ge content. The third layer contains 30-40 at.% Ge to provide high driving current, while the first and second layers with lower Ge content serve as transition zones that maintain interface quality and prevent stacking faults.
Solution Approach 2:
The Ge content parameter is changed gradually across the three SiGe layers rather than being uniform. This parameter gradient (5-20 at.% → 20-30 at.% → 30-40 at.%) allows the structure to achieve high Ge content for productivity while maintaining manufacturing precision through controlled composition transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates or reduces stacking faults, allowing for high Ge content in SiGe regions while improving PMOS device performance.
Implementation Method 1
forming a first SiGe layer on the bottom of the recess which is not covered by the SiGe seed layer, wherein the content of Ge in the first SiGe layer is gradually increased from the bottom to top of the first SiGe layer
Data Source
AI summary
This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.