Embedded SiGe Strain Engineering for CMOS Transistor Mobility
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Solution Overview
Problem
In the fabrication of integrated circuits, particularly in CMOS technology, the continuous reduction of transistor dimensions leads to challenges in maintaining charge carrier mobility and channel controllability, which can offset the advantages of smaller channel lengths, and existing strain engineering techniques primarily focus on enhancing P-channel transistors without effectively improving N-channel transistors.
Innovation Solution
The use of embedded semiconductor alloys, such as silicon/germanium, to induce tensile or compressive strain in N-channel and P-channel transistors respectively, allowing for a single type of semiconductor alloy to enhance the performance of both transistor types, thereby achieving a balanced performance gain between N-channel and P-channel devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If channel length is reduced to increase operating speed, then operating speed is improved, but charge carrier mobility deteriorates
Solution Approach 1:
The patent applies strain engineering by modifying the physical state of the channel region through tensile or compressive strain. This changes the band structure parameters of the semiconductor material, enabling enhanced charge carrier mobility without requiring further channel length reduction. The strain parameter is controlled through epitaxial growth conditions and layer composition.
Solution Approach 2:
The patent uses composite semiconductor structures combining different materials (e.g., SiGe source/drain regions with silicon channel, or inverse configuration) to create differential strain in the channel. This composite approach allows simultaneous optimization of both NMOS and PMOS transistors by selecting appropriate material combinations for each device type.
2Reliability
If conventional strain engineering techniques are applied to enhance P-channel transistors, then P-channel transistor performance is improved, but N-channel transistor performance remains unaffected
Solution Approach 1:
The patent develops a universal strain engineering approach that can enhance both NMOS and PMOS transistors using the same fundamental technique. By controlling the strain type (tensile or compressive) through material selection and structural configuration, the same epitaxial growth process can be applied to both transistor types to achieve performance improvement in both cases.
Solution Approach 2:
The patent applies different strain conditions to different regions: tensile strain is applied to NMOS channels while compressive strain is applied to PMOS channels. This local differentiation is achieved through selective material placement (e.g., SiGe in source/drain regions adjacent to channel) and controlled epitaxial growth, allowing each transistor type to receive optimized strain treatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases electron mobility in N-channel transistors and hole mobility in P-channel transistors, leading to improved overall device performance while maintaining process compatibility with conventional CMOS techniques, thus enhancing the performance of integrated circuits without increasing complexity.
Implementation Method 1
creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region
Implementation Method 2
embedded silicon/germanium (Si/Ge) so as to enhance charge carrier mobility in the channel regions
Data Source
AI summary
By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.