Embedded Si/Ge Strain-Inducing Regions for Transistor Uniformity
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Solution Overview
Problem
The challenge in fabricating integrated circuits is to enhance charge carrier mobility in transistor channel regions while maintaining the integrity of the gate electrode structure, as further reducing the lateral offset of silicon/germanium alloy from the channel region is difficult without compromising the gate integrity, leading to non-uniformities and performance variability in highly scaled transistors.
Innovation Solution
The use of self-limiting deposition behavior in selective epitaxial growth techniques to control the deposition of strain-inducing semiconductor materials, allowing for reduced lateral offset and uniformity in transistor characteristics by forming strain-inducing regions without cavities, and using common spacer configurations for both types of transistors to ensure consistent processing history.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the lateral offset of silicon/germanium alloy from the channel region is reduced to enhance charge carrier mobility, then the mobility increases, but the gate electrode structure integrity is compromised
Solution Approach 1:
The patent applies local quality by forming strain-inducing regions with silicon/germanium alloy only in specific locations adjacent to the channel region, rather than uniformly across the entire structure. This localized approach enables enhanced charge carrier mobility in the channel while maintaining gate electrode integrity by limiting the alloy's proximity to the gate. The strain-inducing regions are precisely positioned to provide local strain enhancement without compromising the gate structure.
2Speed
If the lateral offset is further reduced to improve mobility, then mobility enhancement increases, but process uniformity and manufacturing precision deteriorate
Solution Approach 1:
The patent employs preliminary action by forming offset spacers before depositing the silicon/germanium alloy. These pre-formed spacers establish precise lateral offsets and define the boundaries of strain-inducing regions, ensuring uniformity across the wafer. The offset spacers act as templates that guide subsequent material deposition, maintaining consistent manufacturing precision while achieving the desired reduced lateral offset for mobility enhancement.
Solution Approach 2:
The patent utilizes parameter changes by controlling the lateral offset distance between the silicon/germanium alloy and the channel region. By optimizing this critical dimension parameter, the patent achieves an balance between mobility enhancement and process uniformity. The offset distance is carefully controlled within specific ranges to maximize mobility improvement while maintaining manufacturability and consistency across production batches.
3Productivity
If different spacer configurations are used for different transistor types to optimize individual performance, then individual transistor performance improves, but device complexity and processing variability increase
Solution Approach 1:
The patent applies universality by using a common offset spacer configuration for both NMOS and PMOS transistors. This unified approach simplifies the fabrication process by eliminating the need for different spacer formation steps for different transistor types, thereby reducing device complexity and processing variability. The common spacer structure serves multiple functions: defining lateral offsets, protecting gate electrodes, and establishing uniform strain-inducing region boundaries across all transistor types, while still allowing each transistor type to achieve optimized performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves scalable strain-inducing mechanisms with superior process uniformity, enhancing transistor performance and reducing non-uniformities, particularly in transistors with critical dimensions of 30 nm and less, by maintaining consistent topography and integrity of gate electrode structures.
Implementation Method 1
selective epitaxial growth techniques to control the deposition of strain-inducing semiconductor materials
Implementation Method 2
self-limiting deposition behavior in selective epitaxial growth techniques
Implementation Method 3
creating tensile strain in the channel region... increases the mobility of electrons... compressive strain in the channel region may increase the mobility of holes
Implementation Method 4
modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region
Data Source
AI summary
A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.