Embedded SiGe Stressor S/D Regions for FET Performance
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Solution Overview
Problem
The integration of embedded SiGe into CMOS process flows for FETs is challenging due to the need for precise stress generation, active dopant concentration, and compatibility with stress liners, which affects carrier mobility and device performance.
Innovation Solution
A method involving forming embedded stressor Source/Drain regions with SiGe, a doped layer below the stressor regions adjacent to isolation regions, and a stressor liner over reduced spacers of the FET gate, including epitaxial growth of SiGe and additional boron implantation to enhance stress distribution and dopant concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded SiGe is integrated into CMOS process flow, then carrier mobility and device performance are enhanced, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the stressor region formation with the source/drain region formation by using the same epitaxial growth process to create SiGe regions that serve both as stressors and as source/drain contacts. This integration eliminates separate stressor fabrication steps and simplifies the overall CMOS process flow while maintaining the performance benefits of embedded stress.
Solution Approach 2:
The SiGe regions are designed to perform multiple functions simultaneously: they act as stressor regions to induce compressive stress in the channel, serve as source/drain contact regions for electrical connections, and provide doping regions for carrier injection. This multi-functionality reduces the number of separate structures and processes needed.
2Stress or pressure
If SiGe is embedded into S/D regions, then uniaxial stress is generated in the silicon channel, but compatibility with stress liners becomes challenging
Solution Approach 1:
The patent applies local quality by creating SiGe regions with specific compositional gradients and thickness variations in different locations. The SiGe content and thickness are locally optimized to generate the desired compressive stress in the channel while maintaining compatibility with overlying stress liners in specific regions.
Solution Approach 2:
The patent utilizes parameter changes by varying the SiGe composition ratio, layer thickness, and doping concentration to control the stress characteristics. By adjusting these parameters, the embedded SiGe regions generate appropriate compressive stress while maintaining lattice matching and compatibility with subsequent stress liner deposition.
3Stress or pressure
If the S/D stressor regions are made thicker, then stress generation is enhanced, but external and contact resistances increase
Solution Approach 1:
The patent optimizes the thickness parameter of the SiGe stressor regions to achieve the desired balance. By carefully controlling the thickness within a specific range and using compositional grading, the design enhances stress generation while minimizing the increase in external and contact resistances.
Solution Approach 2:
The patent employs composite material structures by combining SiGe stressor regions with highly doped contact regions and metal silicide contact plugs. This composite approach allows the stressor regions to be sufficiently thick for stress generation while the highly conductive contact regions compensate for resistance increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances FET device performance by creating compressive stress in the channel, improving carrier mobility and reducing external and contact resistances, while simplifying the integration process and maintaining compatibility with stress liners.
Implementation Method 1
SiGe can be embedded into the S/D regions of PFETs to generate uniaxial stress in the silicon channel
Implementation Method 2
epitaxial growth of SiGe
Implementation Method 3
additional boron implantation to enhance stress distribution and dopant concentration
Data Source
AI summary
An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.