Embedded Signal Processing Circuit for Semiconductor Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing testing methods for semiconductor devices, particularly in multichip configurations like SiP and PoP, require expensive high-speed testing devices and are inefficient due to the need for numerous external terminals and complex wiring, limiting the number of devices that can be tested and increasing costs.
Innovation Solution
The integration of a signal processing circuit and a memory circuit within semiconductor devices, where the signal processing circuit performs tests on the memory circuit using a clock signal, eliminating the need for external terminals and simplifying the testing process by using an embedded memory test program, thereby reducing the size and complexity of the test system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If external terminals and complex wiring are used for testing memory circuits, then testing capability is improved, but device size increases and parasitic capacitance increases
Solution Approach 1:
The patent merges the testing function with the signal processing circuit by integrating a test program storage area and test execution logic into the existing semiconductor device structure. The signal processing circuit executes test programs stored in its memory to automatically test memory circuits, eliminating the need for separate external testing terminals and complex wiring.
Solution Approach 2:
The semiconductor device performs self-testing by using its own signal processing circuit to execute test programs that test its memory circuits. The device tests itself without requiring external testing equipment or additional terminals, thereby reducing device size and parasitic capacitance while maintaining full testing capability.
2Difficulty of detecting and measuring
If external terminals and complex wiring are used for testing memory circuits, then testing capability is improved, but power consumption increases
Solution Approach 1:
The testing function is merged with the signal processing circuit, allowing test operations to be performed using the existing internal power supply and circuitry of the semiconductor device. This integration eliminates the need for separate power supplies and external wiring that would increase power consumption.
Solution Approach 2:
The device performs self-testing using its own internal resources, including power supply and processing circuits. This self-service approach eliminates the need for external testing equipment that would consume additional power, thereby reducing overall power consumption while maintaining testing capability.
3Productivity
If multiple devices are mounted on test board, then testing efficiency is improved, but number of devices that can be mounted is limited due to space requirements
Solution Approach 1:
The patent combines multiple testing functions into a single integrated test program that can be executed by the signal processing circuit. This integration allows multiple devices to share the same testing resources and infrastructure, enabling more devices to be mounted on the test board without requiring proportionally more space for testing equipment and wiring.
Solution Approach 2:
The signal processing circuit is designed with universal functionality to execute test programs for various memory circuit configurations. This multi-functionality allows the same circuit and test infrastructure to test multiple different devices, increasing the number of devices that can be mounted on the test board while maintaining high testing efficiency.
Data Source
AI summary
A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.