Embedded Singulated Capacitor Power Core for Low Inductance
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Solution Overview
Problem
Conventional power distribution systems face challenges in reducing impedance and improving voltage response at higher frequencies and lower voltages, leading to power droop and overshoot issues in semiconductor devices, which are not adequately addressed by existing capacitor placements and designs.
Innovation Solution
A power core device with embedded singulated capacitors on the outer layer, connected directly to Vcc and Vss terminals, and a planar capacitor laminate structure that integrates low inductance and high capacitance functions, allowing for improved power distribution and reduced impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If surface mount capacitors are placed close to the IC, then voltage response time is improved, but circuit loop inductance increases
Solution Approach 1:
The patent merges the capacitor structure directly into the PWB laminate, eliminating separate surface mount components. The capacitor electrodes are formed as integrated traces within the board layers, combining the capacitor function with the PCB structure itself, thereby reducing loop inductance while maintaining fast voltage response.
Solution Approach 2:
The patent transitions from surface-mounted capacitors (2D placement on board surface) to embedded capacitors formed within the 3D laminate structure. By forming capacitor electrodes in internal board layers and connecting them through vertical vias, the design utilizes the third dimension to reduce current loop area and inductance.
2Object-affected harmful factors
If large numbers of capacitors are interconnected in parallel, then impedance reduction is improved, but circuit loop inductance increases
Solution Approach 1:
The patent combines multiple capacitor functions into a single integrated laminate structure. Multiple capacitor electrodes are formed in different board layers and connected through vias, creating parallel capacitance paths without requiring separate surface mount components, thus reducing overall loop inductance while maintaining low impedance.
3Ease of manufacture
If capacitors are surface mounted on PWB, then manufacturing is simplified, but voltage response time deteriorates
Solution Approach 1:
The patent segments the capacitor fabrication process from the PWB manufacturing process. Capacitor electrodes are formed as separate trace patterns on capacitor foils, which are then laminated to the PWB. This segmentation allows standard PWB manufacturing techniques to be used while achieving embedded capacitor integration for faster voltage response.
Solution Approach 2:
The capacitor electrodes are pre-formed on capacitor foils before lamination to the PWB. This preliminary action allows the capacitor traces to be precisely patterned and positioned, enabling direct connection to IC power pins through the laminate structure, thereby achieving fast voltage response while using conventional manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables superior power distribution impedance reduction and faster voltage response, accommodating higher IC switching speeds while reducing voltage ripple and eliminating the need for solder joints, thus enhancing reliability and surface real estate usage.
Implementation Method 1
both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively
Data Source
AI summary
A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.