Embedded-Slicer Decision Feedback Equalization for High-Speed ISI
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Solution Overview
Problem
Conventional decision feedback equalizers (DFE) struggle to effectively compensate for inter-symbol interference (ISI) at high data rates due to timing constraints and noise amplification, limiting their performance in high-speed data communication channels.
Innovation Solution
The implementation of a decision feedback equalizer with a dynamic threshold voltage calibration circuitry and self-calibration module that adaptively adjusts the N-tap linear filter coefficients and threshold voltages to reduce ISI without increasing power consumption, using a slicer with embedded feedback loops and current sources to manage timing and noise margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DFE feedback loop timing is used at very high data rates, then the DFE can compensate for ISI, but the feedback loop delay (including slicer settling time, summer amplifier settling time, and storage element settling time) prevents the DFE from meeting timing requirements
Solution Approach 1:
The patent combines the DFE feedback loop functionality with the slicer circuit by embedding the feedback path directly within the slicer structure. This integration eliminates separate feedback loop components and their associated delays, allowing the DFE to meet timing requirements at very high data rates while maintaining effective ISI compensation
Solution Approach 2:
The patent uses preliminary action by pre-charging capacitive nodes and preparing feedback signals before they are needed for decision-making. This advance preparation reduces the critical settling time requirements and allows the feedback loop to operate correctly within the available time budget at high data rates
2Reliability
If CTLE is used to boost high frequency components to remove ISI, then ISI is reduced, but noise is amplified and SNR does not improve
Solution Approach 1:
The patent converts the harmful effect of noise amplification into a benefit by using the amplified noise signal itself as feedback. The DFE structure feeds back the decision-made signal to cancel ISI, and this feedback mechanism inherently handles noise by making decisions based on the dominant signal components while ignoring noise fluctuations
3Reliability
If transmitter FIR equalization or receiver CTLE components are used, then high frequency boosting is achieved, but they are incapable of equalizing reflections caused by impedance mismatch and amplify crosstalk noise
Solution Approach 1:
The patent applies feedback by taking the decided signal from the slicer and feeding it back through delay elements and summer amplifiers to subtract the ISI component from the received signal. This feedback mechanism dynamically adapts to cancel reflections and impedance mismatch effects without amplifying crosstalk noise, as the feedback is based on actual decided symbols rather than amplified received signals
Data Source
AI summary
An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.