Embedded SMT Capacitor Power Core for Low Inductance
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Solution Overview
Problem
Conventional power distribution systems in semiconductor devices face challenges in reducing impedance and improving voltage response at higher frequencies and lower voltages, leading to power droop and overshoot issues that can cause IC malfunctions, as they require complex electrical routing with many SMT capacitors, increasing inductance and impedance.
Innovation Solution
A power core structure is created by embedding SMT discrete chip capacitors and planar capacitor laminates in parallel within a laminate structure, with the planar capacitor laminate serving as a low inductance path to supply charge to the SMT capacitors, allowing for closer placement to ICs and reduced impedance, and integrating high capacitance and low inductance functions within the substrate of printed wiring boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple SMT capacitors are used to reduce impedance, then impedance reduction is improved, but device complexity and inductance increase
Solution Approach 1:
The patent combines multiple capacitor functions into a single integrated power core device. The power core integrates high capacitance and low inductance functions within a single laminate structure, eliminating the need for multiple separate SMT capacitors while maintaining impedance reduction benefits
Solution Approach 2:
The power core device performs multiple functions simultaneously: it provides high capacitance for power storage, low inductance for fast response, and impedance reduction all within a single component. This multi-functional design replaces the need for multiple specialized capacitors
2Speed
If multiple SMT capacitors are placed close to IC, then voltage response is improved, but area occupied increases
Solution Approach 1:
The patent merges multiple capacitor functions into a single integrated power core device. The power core integrates high capacitance and low inductance functions within a single laminate structure, eliminating the need for multiple separate SMT capacitors while maintaining impedance reduction benefits
Solution Approach 2:
The invention transitions from surface-mounted capacitors occupying board area to an embedded laminate structure integrated within the substrate. By moving the capacitance function into the third dimension (embedded layers), the solution conserves valuable surface real estate while maintaining performance
3Quantity of substance
If complex electrical routing is used with many SMT capacitors, then capacitance is increased, but inductance increases reducing effectiveness
Solution Approach 1:
The patent combines multiple capacitor functions into a single integrated power core device. The power core integrates high capacitance and low inductance functions within a single laminate structure, eliminating the need for multiple separate SMT capacitors while maintaining impedance reduction benefits
Solution Approach 2:
The power core acts as an intermediary between the power supply and the IC, providing a low-inductance path for current flow. The integrated laminate structure serves as a mediator that delivers high capacitance without the inductance penalty associated with complex external routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces impedance and improves voltage response, enabling operation of high-speed ICs at lower voltages with reduced noise and ripple, conserving surface real estate and eliminating the need for multiple SMT capacitors, thus enhancing reliability and reducing production costs.
Implementation Method 1
at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor
Implementation Method 2
impedance in conventional circuits is reduced by the use of additional surface mount technology (SMT) capacitors interconnected in parallel
Data Source
AI summary
The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.