Embedded Software Debugging via Register Memory Tracing Database

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Solution Overview

Problem

Current simulators for embedded software debugging in event-driven simulation environments lack non-intrusive interactive debugging capabilities, restricting observability and controllability, and often create atypical system conditions due to running on the same operating system as the application being tested.

Innovation Solution

A system that supports interactive debugging through a processor model with a register and memory tracing sub-module, using simulator breakpoints to capture and store trace information in a database, allowing for the analysis of register and memory value changes, and combining this data with symbolic debugging information for effective variable viewing and breakpoint management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current simulators are used for embedded software debugging, then debugging functionality is provided, but non-intrusive interactive debugging capability is lacking and system conditions become atypical

Engineering Contradiction:
Improvedebugging effectivenessVSAvoidnon-intrusive interactive debugging capability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces a trace information database as an intermediary layer between the processor model and the debugging interface. This database stores trace information about processor states, register values, and memory contents, allowing debuggers to query and analyze system state without directly interfering with processor-hardware model interactions. The intermediary database enables non-intrusive debugging by decoupling the observation mechanism from the processed system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If special model APIs are used for memory and variable viewing, then debugging capability is enhanced, but processor interactions with external hardware models are affected

Engineering Contradiction:
Improvememory and variable viewing capabilityVSAvoidprocessor interactions with hardware models
Core Design Contradiction:
Difficulty of detecting and measuringVSReliability

Solution Approach 1:

The system performs preliminary actions by automatically capturing and storing trace information about processor states, register values, and memory contents in a database during normal operation. This pre-captured data is then available for debugging queries without requiring special API calls that would interrupt or alter processor-hardware model interactions. The preliminary tracing action enables retrospective analysis without real-time interference.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the debugger runs on the same operating system as the application being tested, then system resources are consolidated, but atypical system conditions are created that reduce test effectiveness

Engineering Contradiction:
Improvesystem structureVSAvoidtest effectiveness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent creates a copy of the relevant system state information by storing trace data in a database. The debugger operates on this copied data rather than directly on the running application, allowing analysis of system state without the debugger process interfering with application execution. This copying mechanism enables the debugger to function independently from the application's operating system environment, maintaining typical test conditions while providing comprehensive debugging capability.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10802852B1Method for interactive embedded software debugging through the control of simulation tracing components
Publication Date: 2020.10.13 CADENCE DESIGN SYST INC
  • US10802852B1 patent drawing
  • US10802852B1 patent drawing
  • US10802852B1 patent drawing

AI summary

According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.