Embedded SOI MOS Capacitor Structure for Low Leakage Isolation
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Solution Overview
Problem
As transistor dimensions shrink, leakage becomes a significant issue in MOS capacitors, and the traditional silicon dioxide gate insulating layer is vulnerable to breakdown, necessitating the development of advanced fabrication methods compatible with high-k metal gate processes.
Innovation Solution
The formation of an embedded SOI structure within the MOS capacitor, involving n-type doping, epitaxial layer formation, trench creation, selective silicon lateral etching, and insulation material filling to isolate the capacitor plate from the substrate, reducing leakage by creating a pillar-supported SOI structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the traditional silicon dioxide gate insulating layer is used in MOS capacitors, then the fabrication process is simple and compatible with standard CMOS, but leakage current increases and the gate insulating layer becomes vulnerable to breakdown as transistor dimensions shrink
Solution Approach 1:
The patent embeds an SOI structure within the MOS capacitor, creating a nested configuration where the SOI layer is positioned between the capacitor plate and the substrate. This nested structure provides enhanced isolation and breakdown resistance without requiring a complete redesign of the capacitor architecture, thus improving reliability while maintaining reasonable fabrication complexity
Solution Approach 2:
The patent segments the capacitor structure by introducing a separate SOI layer that isolates the capacitor plate from the substrate. This segmentation creates distinct functional regions: the embedded SOI structure for isolation, the capacitor plate for electrical function, and the substrate for mechanical support. The segmentation enables reduced leakage and improved breakdown resistance while allowing standard CMOS fabrication processes to be used
2Productivity
If transistor dimensions are reduced to increase integration density, then productivity and circuit capacity improve, but leakage current increases significantly
Solution Approach 1:
The patent extracts the isolation function from the bulk substrate by introducing an embedded SOI structure. The SOI layer is selectively formed and positioned to provide electrical isolation between the capacitor plate and the substrate, removing the leakage pathway that would otherwise exist in standard bulk CMOS structures. This extraction of the isolation function enables reduced leakage while maintaining high integration density
Solution Approach 2:
The patent applies local quality by forming the embedded SOI structure only in specific regions where capacitors are located, rather than throughout the entire substrate. The SOI layer is positioned locally at the capacitor plate-substrate interface to provide isolation where needed, while leaving other regions of the substrate unchanged for standard transistor operation. This localized approach reduces leakage in capacitor regions without affecting overall integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces capacitor leakage by isolating the SOI structure from the substrate except at the pillar, enhancing device performance and compatibility with CMOS processes.
Implementation Method 1
The device region is implanted with n-type dopants to form an implanted region and an un-implanted region
Implementation Method 2
An epitaxial layer is formed over the implanted region
Implementation Method 3
A selective silicon lateral etch is performed through the trench to remove the implanted region and form a cavity under the epitaxial layer in the device region. The un-implanted region is retained to form a pillar under the epitaxial layer
Data Source
AI summary
A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.