Embedded Source-Drain Transistor Layout for Lower Channel Resistance

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Solution Overview

Problem

The high resistance in the channel region between the source and the drain of transistors in semiconductor memory devices, such as MRAM units, leads to reduced device performance, especially as transistor dimensions decrease.

Innovation Solution

The semiconductor structure is formed with the source and drain electrodes recessed within the patterned semiconductor layer, reducing the current path length and mitigating high resistance issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If transistor dimensions are decreased to increase integration density, then device capacity is improved, but channel resistance increases leading to reduced device performance

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The source and drain electrodes are configured to extend into the semiconductor layer along the vertical dimension rather than only horizontally. This vertical extension into the semiconductor layer creates additional current flow paths and reduces the effective channel resistance without requiring further reduction in horizontal transistor dimensions, thus maintaining integration density while improving device performance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source and drain electrodes are nested within the semiconductor layer structure, with portions of the electrodes extending into the semiconductor layer. This nesting configuration allows the electrodes to be embedded within the active device region, reducing the current path length through the high-resistance channel region while maintaining compact device footprint

Inventive Principle:

Principle #7Nested doll (Nesting)

2Device complexity

If source and drain electrodes are positioned over the gate dielectric layer, then device structure is simplified, but current path length increases leading to high resistance

Engineering Contradiction:

Improvestructure complexityVSAvoidchannel resistance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Instead of positioning the source and drain electrodes entirely above the gate dielectric layer surface, the invention inverts the conventional approach by having the electrodes extend downward into the semiconductor layer. This inversion allows the electrodes to contact the semiconductor material directly, creating shorter current paths and reducing channel resistance while maintaining structural simplicity

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS12218252B2Semiconductor structure with source and drain electrode embedded within semiconductor layer and manufacturing method thereof

Publication Date: 2025.02.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.