Embedded Source/Drain Fabrication via Sacrificial Mask Recess Shaping
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in creating efficient source/drain structures for transistors, particularly in achieving the necessary stress distribution and size reduction for improved performance and reliability in smaller devices.
Innovation Solution
The method involves forming sigma-shaped recesses between gate patterns on a substrate using directional deposition and isotropic etching, with sacrificial film patterns acting as masks, to create semiconductor patterns that apply tensile or compressive stress to channel regions, enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to create source/drain structures, then manufacturing process is simpler, but stress distribution and device performance are insufficient
Solution Approach 1:
The method performs preliminary actions by forming sacrificial film patterns on the bottom surfaces of recesses before completing the recess formation. These sacrificial patterns are deposited using directional deposition and serve as etch masks during subsequent isotropic etching, enabling precise control over the final recess shape and stress distribution in the source/drain structures.
Solution Approach 2:
Sacrificial film patterns are introduced as intermediary elements that facilitate the formation of complex sigma-shaped recesses. These temporary structures guide the isotropic etching process to achieve the desired undercut geometry, and are later removed to reveal the final source/drain structure with optimized stress characteristics.
2Productivity
If device size is reduced for smaller transistors, then device density increases, but achieving necessary stress distribution becomes more difficult
Solution Approach 1:
The method applies local quality by forming sigma-shaped recesses with specific geometries that create localized stress fields in the source/drain regions. The recesses are positioned and dimensioned to generate appropriate tensile or compressive stress in specific areas of the channel, enabling stress engineering in scaled-down devices without compromising overall device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved stress distribution and performance of semiconductor devices by forming semiconductor patterns with different lattice constants, optimizing the performance of both PMOS and NMOS transistors and enabling smaller device sizes.
Implementation Method 1
A first sacrificial film pattern is formed on a bottom surface of the first recess using a directional deposition process
Implementation Method 2
An isotropic etching process is performed on the first recess using the sacrificial layer as an etch mask to form a second recess
Data Source
AI summary
A method for fabricating a semiconductor device is provided. A first gate pattern and a second gate pattern are adjacent to each other and are formed on an active region of a substrate. The active region is defined by an isolation film. A first recess is formed between the first gate pattern and the second gate pattern. A first sacrificial film pattern is formed on a bottom surface of the first recess using a directional deposition process. A second recess is formed by etching the first recess using the first sacrificial film pattern as a etch mask. The first recess is laterally extended to form the second recess.