Embedded Source/Drain MOS Transistor Leakage Reduction
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Solution Overview
Problem
As semiconductor devices shrink, leakage current from the source and drain regions to the substrate increases, degrading device performance, despite the use of techniques like gate-last and embedded source/drain structures.
Innovation Solution
An embedded source/drain MOS transistor is developed with a stack comprising a dielectric layer and a semiconductor layer, where the semiconductor layer acts as the source/drain region and the dielectric layer isolates it from the substrate, using crystal materials with lattice constants that produce compressive or tensile stress to improve carrier mobility, and the semiconductor layer extends under the gate with specific sidewall morphology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source region and drain region are formed with surfaces higher than the semiconductor substrate surface to reduce contact capacitance, then device performance is improved, but leakage current from source/drain to substrate increases significantly
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the semiconductor layer (source/drain region) and the semiconductor substrate. This dielectric layer acts as a mediator that electrically isolates the source/drain regions from the substrate, thereby reducing leakage current while maintaining the raised source/drain structure for low contact capacitance. The dielectric layer fills the space between the semiconductor layer and substrate, providing the necessary electrical isolation.
Solution Approach 2:
The patent segments the traditional monolithic source/drain structure into multiple distinct layers: a semiconductor layer forming the source/drain region, and a separate dielectric layer providing electrical isolation. This segmentation allows the source/drain structure to maintain its raised configuration for performance optimization while the dielectric layer independently provides the isolation function to reduce leakage current.
2Object-generated harmful factors
If embedded source/drain structure is used to reduce leakage current, then leakage current is reduced, but device complexity increases due to additional formation steps
Solution Approach 1:
The patent merges the formation of the dielectric layer and semiconductor layer into a single integrated process sequence. The dielectric layer is formed first to define the isolation regions, and then the semiconductor layer is deposited to form the source/drain regions. This combined approach achieves leakage current reduction through the embedded structure while streamlining the manufacturing process by coordinating these two layer formations as a unified process flow rather than separate independent steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces leakage current, enhances carrier mobility, and improves device performance by isolating the source/drain regions from the substrate and generating stress in the channel region.
Implementation Method 1
a dielectric layer 24 and a semiconductor layer 25 on the dielectric layer 24... the dielectric layer 24 isolating the semiconductor layer 25 from the semiconductor substrate 20 under it, thereby reducing the leakage current
Implementation Method 2
the material of the dielectric layer 24 and/or the semiconductor layer 25 comprises crystal materials... the dielectric layer and/or the semiconductor layer has a lattice constant larger than that of the semiconductor substrate... produce compressive stress in the channel... produce tensile stress in the channel
Data Source
AI summary
An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.