Embedded Source-Drain Transistors with Graded Germanium Layers
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing carrier mobility in transistors while maintaining low voltage operation, particularly in the fabrication of metal oxide semiconductor field effect transistors (MOSFETs) with embedded source and drain regions.
Innovation Solution
The semiconductor device incorporates a substrate with recesses on both sides of the channel region, featuring a gate insulation layer and a gate electrode, with source and drain regions composed of lower and upper main layers of material having different atomic percentages of Ge, where the lower main layer's bottommost point is higher than the recess bottoms and lower than the gate insulation layer's bottom surface, and the upper main layer's topmost point is higher than the gate insulation layer's bottom surface, ensuring optimal Ge content distribution for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If embedded source and drain regions are formed to improve carrier mobility, then carrier mobility is improved, but manufacturing precision becomes more difficult due to the complex multi-layer Ge structure
Solution Approach 1:
The source and drain regions are segmented into multiple main layers (first main layer, second main layer, third main layer) with different Ge contents arranged vertically. This segmentation allows each layer to contribute differently to carrier mobility while maintaining manufacturing control through standardized deposition processes for each layer.
Solution Approach 2:
Different Ge contents are assigned to different vertical positions within the source and drain regions. The first main layer has a first Ge content, the second main layer has a second Ge content different from the first, and the third main layer has a third Ge content different from the second. This local quality variation optimizes carrier mobility at different depths while managing lattice mismatch locally.
2Speed
If Ge content is increased to improve carrier mobility, then carrier mobility is improved, but defects increase due to crystal lattice mismatch
Solution Approach 1:
The Ge content parameter is changed progressively across different vertical layers. The first main layer has a first Ge content, the second main layer has a second Ge content different from the first, and the third main layer has a third Ge content different from the second. This gradual parameter change reduces sudden lattice mismatch and associated defects while maintaining high carrier mobility.
Solution Approach 2:
The source and drain regions are constructed as composite materials with multiple Ge-containing layers having different Ge contents. This composite structure combines the high mobility benefits of Ge-rich regions with the defect-reduction benefits of Ge-poor regions, creating an optimized overall structure that balances performance and reliability.
Data Source
AI summary
A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer.