Embedded Spiral Inductor Package with Through-Integrated Fan-Out Via
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down inductor packages while maintaining high power conversion efficiency and reducing resistance in current semiconductor packaging technologies, particularly in integrating spiral inductors within smaller form factors.
Innovation Solution
A method of forming a package structure that includes a spiral inductor embedded in a molding material, with a through integrated fan-out via (TIV) and a redistribution layer (RDL) that connects the inductor to semiconductor devices, using a dielectric and magnetic layers to enhance inductance and reduce resistance, and external connectors to manage current paths effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If spiral inductors are integrated in traditional semiconductor packages, then power conversion efficiency can be maintained, but the package size and resistance remain large
Solution Approach 1:
The patent transitions from planar 2D inductor layouts to three-dimensional vertical structures by stacking multiple inductor layers (first inductor layer, second inductor layer) separated by dielectric layers. This vertical integration reduces the lateral footprint while maintaining the magnetic coupling necessary for power conversion efficiency. The through-integrated fan-out via (TIV) structure further enables 3D routing of current paths, allowing compact package design without sacrificing electrical performance.
Solution Approach 2:
The patent employs composite material structures including magnetic layers integrated with dielectric layers to form laminated inductor structures. The magnetic layers (with high permeability materials) are combined with conductive layers to create composite inductor elements that enhance inductance density while reducing resistance. This composite approach allows achieving high power conversion efficiency in a reduced volume by optimizing both magnetic and electrical properties simultaneously.
2Volume of moving object
If package size is reduced for smaller form factor, then integration density increases, but resistance in current paths increases
Solution Approach 1:
The through-integrated fan-out via (TIV) structure utilizes vertical dimension to route current paths through multiple layers, creating shorter and more direct current paths compared to lateral routing in planar designs. The TIV penetrates through dielectric layers to establish electrical connections between different inductor layers and external terminals, reducing the overall current path length and associated resistance despite compact lateral dimensions.
Solution Approach 2:
The patent implements localized high-conductivity regions by placing thick copper or aluminum conductive layers specifically in critical current path areas, such as the TIV structures and inductor terminal connections. These localized high-conductivity zones minimize resistance at key interfaces and current bottlenecks, while the overall package maintains small form factor through optimized material distribution rather than uniform thickening throughout the structure.
3Productivity
If traditional packaging structures are used, then manufacturing processes are simpler, but integration density and power conversion efficiency are limited
Solution Approach 1:
The patent divides the inductor structure into discrete segmented layers (first inductor layer, second inductor layer) separated by dielectric layers, with each layer serving specific functional purposes. This segmentation allows independent optimization of each layer's electrical and magnetic properties, enabling higher integration density through systematic stacking. The through-integrated fan-out via (TIV) is also segmented into portions extending through different dielectric layers, facilitating modular assembly and manufacturing while achieving complex 3D interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of spiral inductors in smaller packages with improved power conversion efficiency and reduced resistance, enabling more compact and efficient semiconductor designs.
Implementation Method 1
a dielectric and magnetic layers to enhance inductance
Implementation Method 2
a through integrated fan-out via (TIV) and a redistribution layer (RDL) that connects the inductor to semiconductor devices
Data Source
AI summary
A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.