Embedded SRAM Macro Layout for Density-Current Tradeoffs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The electronics industry faces challenges in designing integrated circuits (ICs) that require both high-density and high-current memory cells to meet the demands of advanced cache memory requirements, while maintaining low power consumption and efficiency, as existing scaling methods increase manufacturing complexity.
Innovation Solution
The use of FinFET and gate-all-around (GAA) transistors in SRAM cells, with high-density memory cells employing narrower channel regions and high-current memory cells using wider channel widths, along with differential dopant concentrations and write-assist circuitry in high-density cells, to achieve improved stability, power efficiency, and operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC dimensions are reduced to improve production efficiency and lower costs, then manufacturing cost decreases, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the SRAM cell into two distinct types: high-density memory cells with narrower channel regions and high-current memory cells with wider channel widths. This segmentation allows each cell type to be optimized independently for its specific function, enabling the IC to achieve both high density and high current capabilities without requiring further reduction of overall IC dimensions, thereby avoiding increased manufacturing process complexity
Solution Approach 2:
The patent applies local quality by providing different channel widths at different locations within the SRAM cell structure. Specifically, the high-density cells have narrower channels in specific regions while high-current cells have wider channels in corresponding regions. This localized differentiation allows each region to have the precise geometric properties needed for its function, achieving both density and current performance without global scaling that would increase manufacturing complexity
2Quantity of substance
If high-density memory cells are designed with narrower channel regions, then memory density increases, but write margin decreases
Solution Approach 1:
The patent segments the SRAM array into dedicated high-density memory cell regions and high-current memory cell regions. The high-density cells use narrower channel regions to maximize storage capacity, while the high-current cells use wider channel regions to provide sufficient write margin. This spatial segmentation resolves the contradiction by allowing each cell type to be optimized for its primary function without compromise
Solution Approach 2:
The patent changes the channel width parameter differently for high-density versus high-current memory cells. High-density cells employ narrower channel widths (e.g., 10nm) to increase density, while high-current cells employ wider channel widths (e.g., 20nm) to improve write margin. This parameter differentiation allows both density and reliability requirements to be satisfied simultaneously through targeted optimization
3Speed
If high-current memory cells use wider channel widths, then operating speed increases, but area occupied increases
Solution Approach 1:
The patent segments the SRAM macro into specialized high-current cell regions where wider channels provide high operating speed, and high-density cell regions where narrower channels provide compact footprint. This segmentation ensures that the area penalty for high-speed cells is confined to specific regions, while the majority of the array maintains high density
Solution Approach 2:
The patent merges both high-density and high-current SRAM macros within a single IC device, allowing the system to leverage both cell types simultaneously. The high-current cells provide fast operation for critical paths, while the high-density cells provide compact storage for general purposes, achieving overall system optimization without requiring all cells to occupy maximum area
Data Source
AI summary
A semiconductor structure includes first and second SRAM cells disposed over a substrate. Each first SRAM cell includes at least two first p-type transistors and four first n-type transistors. Each first p-type and n-type transistors includes a channel in a single semiconductor fin. Each second SRAM cell includes at least two second p-type transistors and four second n-type transistors. Each second p-type transistors includes a channel in a single semiconductor fin. Each second n-type transistors includes a channel in multiple semiconductor fins. The source/drain regions of the first p-type transistors are doped at a first dopant concentration, the source/drain regions of the second p-type transistors are doped at a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration.