Embedded SRAM Macro Layout for Density and Write Current Balance
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Solution Overview
Problem
The electronics industry faces challenges in manufacturing integrated circuits (ICs) that require both high-density and high-current memory cells to support advanced cache memory requirements, with existing technologies struggling to balance density, power consumption, and performance in complex IC manufacturing processes.
Innovation Solution
The implementation of FinFET and GAA transistors in SRAM cells, with high-density memory cells utilizing narrower channel regions and higher dopant concentrations for improved stability and power efficiency, and high-current memory cells using wider channel widths and lower dopant concentrations for enhanced speed, along with write-assist circuitry in high-density cells to improve write margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If narrower channel regions and higher dopant concentrations are used in memory cells, then cell stability and power efficiency are improved, but write margin deteriorates
Solution Approach 1:
The patent applies local quality by implementing different transistor channel widths within the same memory cell structure. Specifically, the pull-up transistors have narrower channel regions optimized for stability and low power, while the pass-gate transistors have wider channel regions optimized for write performance. This spatial differentiation of transistor dimensions within the cell resolves the contradiction between stability and write margin.
Solution Approach 2:
The patent employs parameter changes by varying the channel width dimension of different transistors within the memory cell. The pull-up transistors use narrower channels (e.g., 12nm) for improved stability, while pass-gate transistors use wider channels (e.g., 16nm) for enhanced write capability. This parameter differentiation across different transistor types within the same cell addresses the technical contradiction.
2Speed
If wider channel widths and lower dopant concentrations are used in memory cells, then write speed is enhanced, but power consumption increases
Solution Approach 1:
The patent applies local quality by assigning different channel width characteristics to different transistor types within the memory cell. Pass-gate transistors receive wider channels for high-speed write operations, while pull-up transistors receive narrower channels for low-power operation. This localized optimization of transistor dimensions resolves the contradiction between write speed and power consumption.
3Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory cell into functionally distinct transistor components with different dimensional characteristics. Rather than uniformly scaling all transistors to the minimum feature size, the design segments the cell into pull-up transistors and pass-gate transistors, each optimized for their specific function. This segmentation allows different portions of the cell to be manufactured with different dimensional requirements, managing manufacturing complexity while maintaining high density.
Data Source
AI summary
A semiconductor structure includes first and second SRAM cells disposed over a substrate. Each first SRAM cell includes at least two first p-type transistors and four first n-type transistors. Each first p-type and n-type transistors includes a channel in a single semiconductor fin. Each second SRAM cell includes at least two second p-type transistors and four second n-type transistors. Each second p-type transistors includes a channel in a single semiconductor fin. Each second n-type transistors includes a channel in multiple semiconductor fins. The source/drain regions of the first p-type transistors are doped at a first dopant concentration, the source/drain regions of the second p-type transistors are doped at a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration.