Embedded SRAM With Selective Dislocation Planes
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Solution Overview
Problem
As integrated circuits scale down, the demand for higher read and write speeds in SRAM cells increases, but achieving sufficient read and write margins becomes more challenging due to the smaller size of SRAM cells, requiring innovative solutions to maintain reliable operations.
Innovation Solution
The formation of transistors with multiple threshold voltages is achieved by selectively creating dislocation planes in FinFETs during manufacturing, allowing for the creation of both high-threshold voltage and low-threshold voltage devices on the same chip, enabling improved performance and stability in SRAM cells without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM cells are scaled down to increase integration density, then productivity and area efficiency are improved, but read and write margins deteriorate making reliable operations more difficult
Solution Approach 1:
The patent applies local quality by creating dislocation planes selectively in specific regions of the semiconductor substrate. By controlling the spatial distribution of dislocation planes, different threshold voltage characteristics are achieved in different locations, allowing SRAM cells to have optimized read and write margins while maintaining scaled-down dimensions for high integration density.
Solution Approach 2:
The patent changes the physical parameter of the semiconductor substrate by introducing dislocation planes, which alter the electrical characteristics (threshold voltage) of transistors. This parameter change enables the SRAM cells to achieve better read and write margins without increasing cell size, thus resolving the contradiction between integration density and operational reliability.
2Speed
If transistors with different threshold voltages are created to optimize SRAM performance, then read and write speeds are improved, but device complexity increases
Solution Approach 1:
The patent uses local quality by forming dislocation planes in specific localized regions of the substrate. This allows certain transistors to have different threshold voltages than others, optimizing read and write speeds for specific SRAM cell functions while keeping the overall device structure relatively simple and manufacturable.
Solution Approach 2:
The patent segments the semiconductor substrate into regions with and without dislocation planes. This segmentation creates transistors with different threshold voltages in a controlled manner, enabling optimized SRAM performance without requiring complete redesign of all transistors, thus managing device complexity effectively.
Data Source
AI summary
A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.