Embedded SRAM Doping Segmentation for Gate Depletion
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Solution Overview
Problem
The aggressive scaling of MOS transistors in embedded static random access memory (SRAM) leads to increased gate depletion region, causing unsymmetrical N+ dosage in common gates, which results in current deviations and higher random single bit (RSB) failure rates due to misalignment and manufacturing deviations during N+ polysilicon doping processes.
Innovation Solution
A method involving ion implantation processes on semiconductor substrates to define conductive device areas, where N+ or P+ ions are implanted in specific transistor areas to form gates, ensuring symmetrical doping and reducing RSB failure rates while maintaining proper transistors' effective capacitance, by skipping N+ ion implantation in the memory cell area and performing it only in the logic area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N+ polysilicon doping process is performed on all transistor gates to reduce gate depletion region, then effective capacitance is improved, but random single bit failure rate increases due to unsymmetrical doping in common gates
Solution Approach 1:
The patent divides the doping process into two segments: (1) a first doping process that dopes only the gates in the logic area, and (2) a second doping process that dopes only the gates in the memory cell area. This segmentation prevents the common gate from receiving unsymmetrical doping, thereby reducing random single bit failures while still improving effective capacitance in both logic and memory transistors.
Solution Approach 2:
The patent performs the first doping process on logic area gates before forming the memory cell structure, and then performs the second doping process on memory cell area gates. This preliminary action ensures that logic transistors receive their doping treatment early, and the subsequent memory doping does not interfere with the symmetry of common gates.
2Reliability
If N+ doping is applied to all gates including memory cell area, then effective capacitance improves, but current deviations occur due to misalignment in memory transistors
Solution Approach 1:
The patent segments the doping operations into two distinct processes with different alignment requirements: the first doping process targets logic area gates with relaxed alignment constraints, while the second doping process targets memory cell area gates with precise alignment to active areas. This eliminates current deviations caused by misalignment in memory transistors while maintaining effective capacitance improvement.
3Area of moving object
If aggressive MOS transistor scaling is performed to increase integration density, then device size is reduced, but gate depletion region increases causing performance degradation
Solution Approach 1:
The patent changes the doping parameter (adding N+ polysilicon to the gate) to compensate for the increased gate depletion region effect caused by aggressive scaling. By modifying the gate's electrical properties through doping, the effective capacitance is improved, which counteracts the performance degradation from scaling while maintaining smaller transistor dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the random single bit failure rate in SRAM while maintaining effective capacitance, preventing current deviations and ensuring reliable data storage by ensuring symmetrical gate doping, thus improving the overall performance of SRAM cells.
Implementation Method 1
performing a first conductive ion implantation process on the exposed first conductive device area in the logic area
Data Source
AI summary
The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.