Embedded Stack Capacitor Layout for Thinner Package Substrates
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Solution Overview
Problem
Current semiconductor packages require thick ceramic capacitors due to thickness limitations, which necessitate embedding them in core layers, preventing their integration into substrate build-up layers and resulting in increased manufacturing costs and complexity.
Innovation Solution
Embedding an integrated stack capacitor (ISC) within the substrate build-up layer during manufacturing, allowing for a thinner core layer and improved electrical performance by matching the ISC's thickness with copper wiring patterns, enabling better dielectric thickness uniformity and mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thick ceramic capacitors are used to meet capacitance requirements, then capacitance density is improved, but substrate thickness increases and integration into build-up layers becomes impossible
Solution Approach 1:
The patent changes the physical parameters of the capacitor by transitioning from thick ceramic capacitors to thin-film integrated stack capacitors with vertical stacking architecture. This parameter change enables high capacitance density while maintaining thin profile suitable for build-up layer integration.
Solution Approach 2:
The patent transitions from planar capacitor布局 to three-dimensional vertical stacking, utilizing the vertical dimension to achieve high capacitance density. The multiple capacitor stacks are arranged vertically within the build-up layer, enabling compact integration without increasing substrate thickness.
2Quantity of substance
If ceramic capacitors are embedded in core layers, then capacitance requirements are met, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the capacitor fabrication process with the existing build-up layer manufacturing process. The integrated stack capacitors are formed using the same semiconductor fabrication steps (deposition, etching, patterning) as the surrounding interconnect structures, eliminating separate capacitor assembly steps and reducing manufacturing complexity.
Solution Approach 2:
The build-up layer manufacturing process itself serves to create the capacitors. The same deposition and patterning steps that form the interconnect structures also form the capacitor electrodes and dielectric layers, allowing the process to create both functional elements simultaneously without additional dedicated capacitor fabrication steps.
3Manufacturing precision
If ISC thickness is matched with copper wiring pattern thickness, then dielectric thickness uniformity is improved, but capacitor design flexibility is constrained
Solution Approach 1:
The patent applies different thickness characteristics to different regions of the capacitor structure. The dielectric layers in the capacitor stacks are formed with precise thickness control matching the build-up layer, while the electrode patterns can vary in size and shape to achieve different capacitance values. This local differentiation maintains thickness uniformity while preserving design flexibility.
Solution Approach 2:
The patent segments the capacitor into multiple identical thin-film stacks, each with controlled thickness matching the build-up layer. By using multiple segments in parallel or series, the overall capacitance can be adjusted while maintaining uniform dielectric thickness across all segments, thus preserving design flexibility through numerical scaling rather than dimensional variation.
Data Source
AI summary
A semiconductor package comprises a core layer, an integrated stack capacitor (ISC) on the core layer, one or more build-up layers on the core layer in which the ISC is embedded, and one or more metal layers on the core layer.