Embedded Strained Drain Source Regions via In Situ Etch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of recesses in advanced transistor elements is complex and prone to non-uniformities, affecting the strain distribution and performance of MOS transistors, due to the need for multiple process steps and high selectivity in etching spacer layers.
Innovation Solution
An in situ etch process is used to pattern sidewall spacers and form recesses adjacent to gate electrodes, reducing selectivity requirements and allowing for a single common etch process, thereby enhancing uniformity and flexibility in forming strained semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple separate etch steps with high selectivity are used to form recesses, then the precision of recess formation is improved, but the process complexity increases
Solution Approach 1:
The patent combines multiple separate etch steps into a single common etch process that simultaneously patterns sidewall spacers and forms recesses. This merging of operations reduces process complexity while maintaining manufacturing precision through careful control of etch parameters and the use of a single etch chemistry that achieves sufficient selectivity for both tasks.
Solution Approach 2:
The single common etch process performs multiple functions: it patterns the sidewall spacers to define the recess boundaries and simultaneously etches the recesses to the required depth. This multi-functional approach eliminates the need for separate etch steps while maintaining the precision required for both operations.
2Manufacturing precision
If multiple etch steps are used to form recesses, then the uniformity of recess formation is improved, but the production time increases
Solution Approach 1:
The patent merges multiple etch steps into a single common etch process that forms both sidewall spacers and recesses in one operation. This reduces production time significantly while maintaining recess uniformity through optimized etch parameters, single-chamber processing, and careful control of etch depth and selectivity.
Solution Approach 2:
The single common etch process performs continuous useful action by simultaneously patterning sidewall spacers and forming recesses without interrupting the etch chemistry or transferring wafers between chambers. This continuous process reduces production time while maintaining uniformity through consistent process conditions throughout the entire etch sequence.
3Manufacturing precision
If lithographically patterned hard masks are used, then the precision of recess positioning is improved, but the process complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the lithographically patterned hard mask step from the process flow. Instead of using separate lithography and hard mask formation steps, the methodology uses self-aligned spacer formation where the spacers themselves define the recess positions, achieving sufficient positioning precision without the added complexity and cost of hard masks.
Solution Approach 2:
The sidewall spacers serve a dual function: they act as both the patterning definition (replacing hard masks) and as the structural element that defines recess boundaries. This self-service approach where the spacer structure performs both positioning and boundary definition functions eliminates the need for separate hard mask layers while maintaining positioning precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, improves uniformity, and reduces production costs by eliminating the need for multiple etch steps and lithographically patterned hard masks, while maintaining high device performance and flexibility in forming different strained semiconductor materials.
Implementation Method 1
performing an in situ etch process for etching the spacer layer and the semiconductor layer to form sidewall spacers on sidewalls of the gate electrode and a recess in the semiconductor layer adjacent to the sidewall spacers
Implementation Method 2
enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region... producing a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively
Data Source
AI summary
By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.