Embedded Stress-Inducing Layers in Transistor Source/Drain Cavities
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In CMOS manufacturing, the growth of silicon/germanium material at the shallow trench isolation (STI) edge is incomplete, leading to 'ski-sloped' areas and inadequate silicidation, resulting in contact failures and device malfunctions due to insufficient thickness of the silicon/germanium compound for proper silicide growth.
Innovation Solution
The method involves forming cavities in the semiconductor layer through openings in the interlayer dielectric, filling these cavities with a different semiconductor material like a silicon/germanium compound, and subsequently performing silicidation to ensure uniform growth and reliable contact formation, avoiding growth issues at the STI edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon/germanium material is grown at the STI edge to induce strain in the channel region, then charge carrier mobility is improved, but the material growth becomes incomplete at the STI edge creating 'ski-sloped' areas
Solution Approach 1:
The source/drain regions are divided into two distinct parts: a first source/drain region formed in the semiconductor layer and a second source/drain region formed as an embedded semiconductor material in cavities. This segmentation allows the embedded material to be isolated from the STI edge problem while still providing the desired strain effect in the channel region.
Solution Approach 2:
The embedded semiconductor material acts as an intermediary stress-inducing layer that transfers strain to the channel region without directly contacting the STI edge. By forming this material in cavities within the semiconductor layer rather than at the STI interface, the patent eliminates the growth completion issue while maintaining the strain transfer function.
2Reliability
If silicon/germanium compound is formed to provide compressive strain, then hole mobility in P-type transistors is enhanced, but the compound thickness is insufficient for proper silicide growth
Solution Approach 1:
The embedded semiconductor material is formed with sufficient thickness in the cavity structure before any silicidation attempts. The cavity configuration ensures that the material achieves the required thickness for proper silicide growth while still being positioned to induce strain in the channel region.
Solution Approach 2:
The patent transitions from forming a thin lateral layer at the STI edge to forming a vertically-oriented embedded structure in cavities. This dimensional change allows the material to achieve sufficient thickness in the vertical direction while maintaining its strain-inducing function in the horizontal plane.
3Speed
If channel length is reduced to increase operating speed, then transistor switching speed is improved, but charge carrier mobility degradation occurs
Solution Approach 1:
The patent changes the physical state of the source/drain regions by embedding semiconductor materials with different lattice constants. This parameter change induces strain in the channel region, which compensates for the mobility degradation that would otherwise result from reduced channel length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for uniform growth of embedded semiconductor materials, enhancing transistor performance by inducing strain in the channel region and ensuring reliable contact formation, thereby reducing device failures and improving conductivity.
Implementation Method 1
creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes
Implementation Method 2
the silicon/germanium material may be formed on the basis of the silicon lattice spacing, thereby resulting in a strained silicon/germanium crystal lattice
Data Source
AI summary
A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.