Embedded Stripline Package Substrate for Compact 50 GHz RF Routing
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Solution Overview
Problem
Existing semiconductor device packaging technologies face challenges in minimizing printed circuit board area and system costs while accommodating high transmission speeds required for applications like vehicular radar systems and high-speed memory controllers.
Innovation Solution
A device package substrate structure is developed, featuring a coreless embedded trace substrate with a conductive layer serving as a ground plane for an embedded signal line, forming a stripline capable of carrying RF signals with frequencies up to 50 GHz and higher.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional PCB structures are used to accommodate high transmission speed circuitry, then transmission speed requirements are met, but printed circuit board area and system costs increase significantly
Solution Approach 1:
The patent transitions from traditional two-dimensional surface traces to three-dimensional embedded stripline structures within the substrate. By embedding signal lines between ground planes in the Z-dimension, the design achieves high-frequency transmission capabilities while maintaining a compact two-dimensional footprint on the PCB surface.
Solution Approach 2:
The patent implements nested ground planes surrounding embedded signal lines, creating a shielded stripline structure. The signal line is nested between multiple ground planes and conductive shields, providing electromagnetic shielding and maintaining signal integrity at high frequencies without increasing external dimensions.
2Speed
If traditional PCB structures are used to accommodate high transmission speed circuitry, then transmission speed requirements are met, but system costs increase significantly
Solution Approach 1:
The patent combines multiple functions into the substrate structure itself: the substrate provides mechanical support, electrical grounding, signal transmission, and electromagnetic shielding simultaneously. By integrating ground planes and signal lines into a single substrate assembly rather than separate PCB layers, manufacturing complexity and cost are reduced while achieving high-frequency performance.
Solution Approach 2:
The patent changes the physical parameters of the transmission structure by embedding signal lines within the substrate rather than routing them on the surface. This structural parameter change enables higher frequency operation (50 GHz and above) while using standard manufacturing processes, avoiding the need for expensive specialized high-frequency PCB materials and fabrication techniques.
3Area of stationary object
If compact footprint is maintained, then PCB area is minimized, but high-frequency RF signal transmission capability is limited
Solution Approach 1:
The patent uses the third dimension (depth within substrate) to achieve high-frequency transmission characteristics without increasing surface area. Embedded striplines positioned between ground planes in the vertical dimension provide controlled impedance and shielding necessary for 50 GHz+ operation while maintaining a compact planar footprint.
Solution Approach 2:
The patent applies different structural qualities to different regions: embedded signal lines with surrounding ground planes are created in specific local areas where high-frequency transmission is needed, while other areas of the substrate can maintain simpler structures. This localized optimization achieves high-frequency capability only where required, minimizing overall footprint.
Data Source
AI summary
A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.