Embedded STT Memory Fabrication with ATP Planarization
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Solution Overview
Problem
The integration of spin transfer torque (STT) memory into processing units faces challenges such as wafer warpage, device performance degradation, and surface roughness issues due to high-temperature processing, which affect the thermal stability and access speed of the memory.
Innovation Solution
The method involves depositing a dielectric layer, forming vias, and using chemical mechanical polishing (CMP) to create a smooth surface for an adhesion and topography planarization (ATP) layer, followed by the deposition of a magnetic tunnel junction (MTJ) film layer, with annealing in forming gas to manage thermal stress and improve interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (400°C) is used to manufacture multi-metal layers of the processing unit, then the logic circuit performance is improved, but wafer warpage and surface roughness occur causing memory yield loss
Solution Approach 1:
The patent divides the memory fabrication process into two distinct temperature stages: (1) high-temperature processing for logic circuit metal layers, and (2) low-temperature processing for MTJ memory layers. This segmentation allows each stage to be optimized independently, preventing thermal damage to the MTJ interface while maintaining logic circuit performance.
Solution Approach 2:
The patent performs preliminary low-temperature annealing (300-360°C for 1-2 hours) on the MTJ free layer before final high-temperature processing. This preliminary action pre-establishes the magnetic anisotropy and interface structure, making the MTJ layer more resistant to subsequent thermal stress and preventing warpage during final processing.
2Manufacturing precision
If low B composition CoxFeyBz film is used for PMA STT, then structure matching to MgO is improved, but B diffusion at 400°C causes lower MR and device thermal stability
Solution Approach 1:
The patent changes the processing temperature parameter from the conventional 400°C to a lower range (300-360°C) for MTJ annealing. This parameter change prevents B diffusion while maintaining the low B composition (xB < 0.15) needed for optimal PMA interface structure, thereby preserving both structure matching and device thermal stability.
Solution Approach 2:
The patent applies different quality requirements to different regions: the MTJ interface region uses low B composition CoxFeyBz for optimal magnetic anisotropy, while the overall processing temperature is controlled locally at 300-360°C during MTJ fabrication to prevent B diffusion. This local quality approach allows optimization of each region's properties without compromising the other.
3Manufacturing precision
If multiple CMP steps are performed to achieve smooth surfaces for MTJ deposition, then surface roughness is reduced, but manufacturing complexity and process time increase
Solution Approach 1:
The patent introduces an ATP layer as a cushioning intermediate layer between the dielectric and MTJ layers. This layer compensates for surface roughness and topography variations, reducing the stringency of CMP requirements and allowing acceptable surface quality with fewer CMP steps, thereby simplifying the overall process.
Solution Approach 2:
The ATP layer serves as an intermediary between the underlying dielectric structure and the MTJ film. It mediates the interface quality by providing a smooth, adherent surface for MTJ deposition even when the underlying dielectric has moderate roughness, reducing the need for aggressive CMP processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the thermal stability and access speed of STT memory while reducing wafer warpage and surface roughness, enabling the fabrication of high-density, low-power memory with improved endurance and access speed.
Implementation Method 1
performing chemical mechanical polishing (CMP) on the second surface using a high selectivity slurry until the first surface is exposed
Implementation Method 2
annealing in a forming gas after step (i) and before step (ii)
Implementation Method 3
depositing a dielectric layer having a first surface on a metal landing pad of a logic circuit of a processing unit
Data Source
AI summary
Systems and methods for forming embedded memory in a processing unit. The methods include: depositing a dielectric layer on a metal landing pad of a logic circuit of a processing unit; opening vias in the dielectric layer; filling in the vias; performing chemical mechanical polishing (CMP); depositing an adhesion and topography planarization (ATP) layer; etching away portions of the ATP layer; filling in with inter layer dielectric (ILD) materials; performing CMP; depositing a MTJ film layer; patterning and etching away portions of the MTJ film layer; filling in with dielectric materials; performing CMP; and forming a bit line on the top layer. The methods may also include annealing in a forming gas during different steps of the above processed to reduce the high stress from the making of multi-metal layers of the processing unit at high temperature. This may prevent wafer warpage and/or significant topography in the fabrication process.