Embedded STT-MRAM Logic Chip with Offset MTJ Sidewalls
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Solution Overview
Problem
Traditional charge-based memory technologies, such as DRAM and NAND Flash, face scalability issues with precise charge placement and sensing at sub-20 nm technology nodes, making it challenging to embed memory directly onto high-performance logic chips.
Innovation Solution
The integration of spin-torque transfer magnetoresistive random access memory (STT-MRAM) within logic chips, utilizing magnetic tunnel junctions (MTJs) with specific layer structures and Inter-Layer Dielectric (ILD) materials, allows for scalable memory solutions that overcome the limitations of traditional charge-based memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional charge-based memory technologies (DRAM, NAND Flash) are used for embedding memory on logic chips, then memory integration is achieved, but scalability issues arise at sub-20 nm technology nodes due to precise charge placement and sensing requirements
Solution Approach 1:
The patent transitions from charge-based memory parameters to magnetoresistive parameters. Instead of relying on precise charge placement and sensing, the invention uses magnetic tunnel junctions where information is stored as magnetic states (parallel or antiparallel magnetization) that are read through resistance changes. This parameter change from electrical charge to magnetic moment eliminates the scaling limitations of charge-based memory at sub-20 nm nodes.
Solution Approach 2:
The invention replaces the electrical/charge-based memory mechanism with a magnetoresistive mechanism. Magnetic tunnel junctions use spin-polarized electron transport through a tunnel barrier to store and read data, substituting the charge trapping and sensing mechanism of traditional memory with a magnetic field-based mechanism that is not subject to the same scaling constraints.
2Speed
If memory is embedded directly onto logic chips, then wider buses and higher operation speeds are enabled, but traditional charge-based memory technologies face scalability limitations
Solution Approach 1:
By changing the fundamental operating parameter from charge to magnetoresistance, the patent enables memory structures that can be scaled to sub-20 nm technology nodes while maintaining high-speed operation. The magnetoresistive mechanism allows for faster write speeds through spin-transfer torque and provides excellent retention characteristics, making the memory adaptable to future technology nodes.
3Reliability
If magnetic tunnel junctions are integrated with logic circuits, then resistivity-based information storage overcomes charge placement issues, but different ILD materials are required for memory and logic areas
Solution Approach 1:
The patent applies different Inter-Layer Dielectric materials to different functional areas of the chip. The memory area uses a first ILD material optimized for magnetoresistive memory structures, while the logic area uses a second ILD material optimized for high-performance logic circuits. This local differentiation allows each area to have the optimal material properties for its function while integrating both on the same chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the embedding of memory within logic chips, meeting stringent RC delay requirements and improving performance by using resistivity as the information carrier, thus addressing scalability issues and enhancing operational speeds.
Implementation Method 1
utilizing magnetic tunnel junctions (MTJs) with specific layer structures and Inter-Layer Dielectric (ILD) materials, allows for scalable memory solutions that overcome the limitations of traditional charge-based memories
Data Source
AI summary
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.