Embedded Substrate Capacitor with Discontinuous Metal Plane
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Solution Overview
Problem
Conventional embedded package substrates with capacitors face high parasitic inductance and resistance due to limited via placement, which increases the footprint and reduces the efficiency of current delivery to integrated circuits.
Innovation Solution
A package substrate with an embedded capacitor that features a discontinuous metal plane, allowing direct contact between electrode pads and the metal plane, and increased flexibility in via placement, reducing loop inductance and parasitic resistance by enabling more vias and better current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vias are limited to electrode footprints in conventional EPS capacitors, then the capacitor structure is simple, but the parasitic inductance and resistance increase
Solution Approach 1:
The patent extends via placement from the conventional two-dimensional electrode footprint area to a three-dimensional discontinuous metal plane that spans multiple layers and locations. This dimensional expansion allows vias to be distributed across a larger spatial volume, increasing the number of current paths without complicating the capacitor structure itself.
Solution Approach 2:
The patent segments the continuous metal plane into multiple discontinuous segments across different layers, with vias strategically placed at various segments. This segmentation creates multiple parallel current paths from the capacitor electrodes to the power ground plane, reducing the inductance and resistance of each individual via path while maintaining structural simplicity.
2Reliability
If decoupling capacitors are mounted on the circuit board, then the parasitic inductance is reduced, but the circuit board footprint increases
Solution Approach 1:
The patent embeds the decoupling capacitor within the package substrate itself, nesting it among the metal layers and routing structures. This nesting approach integrates the capacitor into the existing substrate architecture, eliminating the need for separate board-mounted capacitor locations while maintaining low parasitic inductance through direct coupling to the power ground plane.
Solution Approach 2:
The patent transitions from two-dimensional board-mounted capacitor placement to three-dimensional embedding within the substrate layers. By utilizing the vertical dimension and embedding the capacitor within the substrate structure, the solution achieves low parasitic inductance without consuming additional circuit board footprint area.
3Reliability
If decoupling capacitors are placed close to the die, then the parasitic resistance is reduced, but the package substrate footprint increases
Solution Approach 1:
The patent embeds the decoupling capacitor directly within the package substrate, nesting it among the metal layers and routing structures. This integration allows the capacitor to be positioned in immediate proximity to the die without requiring additional footprint area, as the capacitor utilizes space within the substrate's internal volume rather than occupying surface area.
Solution Approach 2:
The patent utilizes the third dimension by embedding the capacitor within the substrate layers rather than placing it on the surface. This vertical integration enables close coupling to the die for reduced parasitic resistance while maintaining a compact package substrate footprint, as the capacitor occupies vertical space rather than horizontal area.
Data Source
AI summary
A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.