Embedded Substrate Circuit Carrier for Z-Axis Height Reduction
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Solution Overview
Problem
The challenge in the field of chip package structures is to minimize the Z-axis height while integrating multiple chips, as traditional interposers limit the miniaturization and thinning of electronic products.
Innovation Solution
A circuit carrier with an embedded substrate is designed, featuring a trench for embedding a substrate with second bumps, allowing multiple chips to be connected through first and second bumps, thereby reducing the overall thickness and package volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interposers are used to connect chips on a circuit carrier, then chip interconnection is achieved, but the Z-axis height of the package structure increases
Solution Approach 1:
The embedded substrate is placed inside a trench formed in the circuit carrier, nesting one structure within another. This allows the substrate to be embedded rather than stacked, reducing the overall Z-axis height while maintaining chip interconnection capability through the embedded configuration
Solution Approach 2:
Instead of increasing connection capability in the vertical dimension (adding more interposer layers), the invention transitions to horizontal embedding within the circuit carrier plane. The trench allows the substrate to be positioned at a specific depth, utilizing the X-Y plane more effectively to reduce Z-axis height
2Adaptability or versatility
If multiple chips are integrated using traditional interposer structures, then chip integration is achieved, but the package volume increases
Solution Approach 1:
By nesting the substrate within the trench of the circuit carrier, the package structure achieves higher integration density. Multiple chips can be mounted on the embedded substrate and circuit carrier in a more compact arrangement, reducing overall package volume while maintaining versatility
Solution Approach 2:
The invention merges the circuit carrier and substrate into a single integrated structure where the substrate is embedded within the carrier. This consolidation eliminates the need for separate interposer components, reducing package volume while achieving multiple chip integration
Data Source
AI summary
A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.