Embedded Component Substrate Impedance Reduction via 3D Vias
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Solution Overview
Problem
Existing substrates with embedded electronic components face challenges in minimizing impedance in the connection paths to external devices, limiting the full performance potential of semiconductor chips and other components.
Innovation Solution
A substrate design featuring multiple insulating layers and vias that form an electrical loop, with specific dimensions and overlap configurations to reduce impedance, including a first insulating layer with a cavity for the electronic component, and build-up insulating layers with circuit patterns and vias connecting the external electrode to the circuit patterns, forming an electrical loop to decrease impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If electronic components are embedded in the substrate, then miniaturization and slimness are achieved, but impedance of connection paths increases
Solution Approach 1:
The patent transitions from planar two-dimensional circuit patterns to three-dimensional multi-layered circuit patterns with vias connecting different layers. This dimensional change allows current to flow through multiple paths in the vertical direction, reducing impedance while maintaining compact horizontal footprint. The build-up insulating layers and embedded vias create a 3D network that decreases path resistance without increasing overall substrate volume.
Solution Approach 2:
The patent divides the connection path into multiple segmented sections using separate insulating layers and circuit patterns. Instead of a single long trace, the current path is segmented into multiple shorter segments connected by vias, with each segment optimized for specific electrical characteristics. This segmentation reduces overall impedance by distributing the current flow across multiple low-impedance paths.
2Reliability
If distance between decoupling capacitor and semiconductor chip is minimized, then power stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates the decoupling capacitor and its connection paths into the substrate manufacturing process itself, rather than adding them separately afterward. The capacitor is embedded within the multi-layered structure during substrate fabrication, with vias and circuit patterns pre-formed to connect it to the semiconductor chip mounting area. This preliminary integration ensures precise positioning without requiring additional high-precision placement steps.
Solution Approach 2:
The patent merges the decoupling capacitor, its connection paths, and the semiconductor chip mounting structure into a single integrated substrate assembly. The capacitor is positioned in close proximity to the chip mounting area, with direct via connections minimizing the distance between them. This merging eliminates the need for separate component placement and reduces the distance to less than 1mm, improving power stability while simplifying manufacturing.
3Object-affected harmful factors
If multiple insulating layers and vias are added to decrease impedance, then device complexity increases
Solution Approach 1:
The patent designs the multi-layered insulating structure and vias to serve multiple functions simultaneously. The build-up insulating layers provide both electrical insulation and mechanical support, while the vias serve as both connection paths and structural elements. The circuit patterns on different layers are designed to perform multiple electrical functions (signal routing, power distribution, impedance matching) within the same physical structure, reducing overall device complexity despite the multi-layered configuration.
Data Source
AI summary
A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.