Embedded Package Substrate Wiring for Ultra-Fine Line Pitch

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Solution Overview

Problem

Conventional package substrates face limitations in thinning and high-density wiring due to traditional manufacturing processes, leading to increased yield loss and difficulty in reducing the number of wiring layers, which hinders the achievement of thin, high-functionality semiconductor devices.

Innovation Solution

The package substrate embeds conductive traces within an insulating layer with ultra-fine line width/line pitch specifications, reducing the number of total wiring layers and improving yield by forming conductive traces with 7 microns/10 microns line width/line pitch, and optionally including a circuit structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional manufacturing processes with larger line width/line pitch are used, then manufacturing complexity is reduced, but wiring density cannot meet thinning requirements

Engineering Contradiction:

Improveline width/line pitchVSAvoidnumber of wiring layers

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent transitions from planar wiring layers to three-dimensional embedded conductive traces within the insulating layer. This dimensional change allows conductive paths to be formed inside the substrate thickness, enabling ultra-fine line width/line pitch (7 microns/10 microns) without increasing the number of wiring layers, thus achieving high wiring density while maintaining manufacturing feasibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple circuit layers are fabricated to achieve required product functions, then functionality is improved, but yield loss increases

Engineering Contradiction:

Improveproduct functionalityVSAvoidmanufacturing yield

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the conductive paths into embedded traces within the insulating layer and separate through-vias. This segmentation allows each component to be optimized independently - the embedded traces achieve ultra-fine pitch with high yield, while through-vias provide vertical interconnects. The separation eliminates the compounding yield loss associated with building multiple stacked circuit layers.

Inventive Principle:

Principle #1Segmentation

3Length of stationary object

If the number of wiring layers is reduced to meet thinning requirements, then substrate thickness is reduced, but wiring density must be increased

Engineering Contradiction:

Improvesubstrate thicknessVSAvoidwiring density

Core Design Contradiction:

Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent embeds conductive traces within the insulating layer, nesting the conductive elements inside the substrate structure rather than stacking layers externally. This nesting approach achieves high wiring density within the available thickness by utilizing the volumetric space of the insulating layer, allowing ultra-fine trace pitch (7 microns/10 microns) without increasing overall substrate thickness.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20260026377A1Package substrate and manufacturing method thereof

Publication Date: 2026.01.22 SILICONWARE PRECISION IND CO LTD

AI summary

A package substrate is provided, in which at least one conductive trace is embedded in an insulating layer having a conductive through via and is electrically connected to the conductive through via, thereby facilitating the manufacture of the conductive trace with ultra-fine line width/line pitch specifications. Therefore, the wiring density can be increased in accordance with the requirements of the product functions.