Embedded High-Density Substrate Routing for Localized I/O Bottlenecks
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high density substrate routing due to limitations in lithography and plating processes, resulting in lower routing densities that lead to larger substrate areas dedicated to I/O and decreased system and power performance.
Innovation Solution
Embedding high density interconnect elements within a substrate medium, allowing localized high bandwidth chip-to-chip interconnects and enabling chip-level routing densities without requiring major fabrication process changes, while using less expensive lithography and plating processes for conventional routing where high density is not needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and plating processes are used for substrate routing, then manufacturing cost is reduced and process simplicity is maintained, but routing density is limited and I/O area increases
Solution Approach 1:
The substrate is divided into multiple routing regions with different density requirements. High-density interconnect elements are embedded only in specific regions where high routing density is needed, while other regions use conventional low-density routing. This segmentation allows the system to achieve high routing density where necessary without requiring the entire substrate to use complex high-density fabrication processes.
Solution Approach 2:
Different routing densities are implemented in different regions of the substrate based on local requirements. The high-density interconnect elements are selectively embedded in regions requiring high bandwidth, while conventional routing is used in regions with lower density needs. This local quality approach optimizes performance where needed while maintaining manufacturing simplicity elsewhere.
2Productivity
If high density interconnect elements are embedded in the substrate, then routing density and system performance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of implementing high-density routing across the entire substrate, the invention applies high-density interconnect elements only partially, in specific regions where high performance is required. This partial action approach achieves the necessary system performance improvement without incurring the full manufacturing complexity and cost of complete high-density routing throughout the substrate.
3Area of stationary object
If substrate routing density is increased to match chip-level density, then I/O area is reduced and power performance improves, but lithography and plating process requirements become more stringent and costly
Solution Approach 1:
The substrate routing is segmented into high-density and low-density regions. High-density interconnect elements are embedded only in specific areas where high routing density is required to reduce I/O area, while conventional routing is used in other areas. This segmentation allows reduction of I/O area without requiring the entire substrate to meet stringent high-resolution lithography requirements.
Data Source
AI summary
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.