Embedded Component Substrate Sidewall Wiring for High-Density Interconnects
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Solution Overview
Problem
The technology of embedded component substrates faces challenges in meeting the requirements of high-density wiring, particularly in reducing the package size and optimizing the transmission path between embedded electronic components and chips, while maintaining performance and miniaturization.
Innovation Solution
The embedded component substrate includes a substrate with cavities or through holes where electronic components are formed, and a first wiring layer is created between the component and the substrate's sidewalls, extending from the surface to directly contact the component, facilitating efficient signal transmission and reducing package volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If electronic components are embedded in the substrate to reduce package size and transmission path, then the package volume and transmission path length are reduced, but the wiring density and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by extending wiring layers vertically along the sidewalls of cavities and through-holes. This dimensional change allows multiple wiring layers to be stacked vertically, significantly increasing wiring density without expanding the horizontal package footprint, thus resolving the contradiction between reduced package volume and increased wiring density requirements.
Solution Approach 2:
The patent implements nested wiring structures where multiple wiring layers are embedded within and along the sidewalls of cavities and through-holes. The first wiring layer is formed within cavity sidewalls, while subsequent wiring layers are formed in later etched cavities and through-holes, creating a nested configuration that maximizes wiring capacity within the embedded component substrate volume.
2Reliability
If wiring layers are extended to sidewalls of cavities to increase contact area, then the electrical connection reliability is improved, but the substrate area and manufacturing difficulty increase
Solution Approach 1:
The wiring layers are extended vertically along the sidewalls of cavities and through-holes rather than spreading horizontally across the substrate surface. This vertical extension into the third dimension increases the contact area between wiring layers and embedded components without consuming additional substrate area, thereby improving electrical connection reliability while maintaining compact substrate footprint.
Solution Approach 2:
The patent utilizes the cavity and through-hole structures as porous-like spaces that accommodate wiring layers along their sidewalls. These cavities and through-holes provide three-dimensional pathways for wiring layers to extend and contact embedded components, effectively increasing connection area without requiring additional planar substrate area.
3Quantity of substance
If multiple wiring layers are formed in three-dimensional space to achieve high-density wiring, then the wiring capacity is increased, but the manufacturing precision and process complexity increase
Solution Approach 1:
The patent performs preliminary actions by first forming cavities and through-holes in the substrate, then forming adhesion layers and seed layers on the sidewalls of these structures before forming the wiring layers. This preliminary preparation of the substrate structure and surface treatment ensures that subsequent wiring layer formation can be precisely controlled, thereby achieving high wiring capacity with maintained manufacturing precision.
Solution Approach 2:
The patent introduces adhesion layers and seed layers as intermediary layers between the substrate/cavity structures and the final wiring layers. These intermediary layers facilitate precise and controlled formation of wiring layers on complex three-dimensional surfaces, enabling high-density wiring while maintaining manufacturing precision through standardized deposition processes.
Data Source
AI summary
An embedded component substrate and methods for fabricating the same are provided. The embedded component substrate includes a substrate having at least one cavity, a first surface, and a second surface. The embedded component substrate also includes at least one electronic component formed in the at least one cavity. The embedded component substrate also includes a first wiring layer formed in the space between a sidewall of the at least one electronic component and a sidewall of the at least one cavity. The first wiring layer extends from the first surface of the substrate to the sidewall of the at least one cavity, and directly contacts the at least one electronic component.