Embedded Substrate Through-Chip Via Yield Optimization
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Solution Overview
Problem
The challenge lies in manufacturing a small, thin semiconductor element-embedded substrate with a high yield, as existing techniques face difficulties in densifying vias due to high aspect ratios and yield degradation, particularly in the chip layering technique using TSVs, which affects the overall chip yield and is restricted by layout constraints and limited pin configurations in package layering techniques.
Innovation Solution
A semiconductor element-embedded substrate with a through-chip via connecting upper and lower surface terminals, allowing for a multilayer interconnection structure and the use of TSV chips with narrower pitches and higher aspect ratios, enabling independent manufacturing and integration of IC and TSV chips to enhance yield and reduce warpage, while using lateral-to-chip vias for power and ground applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are formed in a region where LSI circuits are not present, then the chip layering technique can be implemented, but layout constraints and keep-out zones limit the densification of TSVs
Solution Approach 1:
The substrate is divided into a first substrate and a second substrate, with TSVs formed only in the second substrate. This segmentation allows TSV formation to proceed without being constrained by circuit layout requirements in the first substrate, thereby eliminating keep-out zone limitations while maintaining circuit functionality.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first substrate and the second substrate. This insulating layer enables electrical isolation and provides a suitable medium for forming TSVs through the second substrate without interfering with the LSI circuits in the first substrate, thus resolving the layout constraint issue.
2Productivity
If the aspect ratio of vias is increased to enable densification, then via density improves, but it becomes more difficult to form holes and fill conductive material
Solution Approach 1:
The via formation process is relocated to the second substrate, allowing TSVs to be formed vertically through the second substrate rather than through the entire package structure. This dimensional reorganization enables higher aspect ratios while maintaining manufacturability, as the hole formation and filling processes occur in a more accessible location.
Solution Approach 2:
The second substrate is prepared in advance with appropriate thickness and material properties before TSV formation. This preliminary preparation ensures that the via formation process can proceed smoothly with high aspect ratios, as the substrate is pre-configured to facilitate hole formation and conductive material filling.
3Area of moving object
If chip size is reduced to accommodate future logic LSIs, then integration density improves, but the technique has difficulty in densifying TSVs
Solution Approach 1:
By separating the substrate into two distinct layers with TSVs formed only in the second substrate, the design allows independent optimization of chip size and TSV density. The first substrate can be miniaturized for future logic LSIs while the second substrate provides dedicated space for dense TSV arrangement, eliminating the trade-off between chip size reduction and TSV densification.
4Reliability
If wire bonding or solder bumps are used for chip interconnection, then yield rate improves, but connection terminals are limited to peripheral parts and stacking more than three chips is difficult
Solution Approach 1:
The invention transitions from peripheral connection methods (wire bonding, solder bumps) to through-substrate vertical interconnection. TSVs provide direct vertical pathways through the second substrate, enabling connection terminals to be distributed across the entire substrate area rather than being confined to peripheral regions. This dimensional change in interconnection architecture supports both high yield and increased chip stacking capability.
Data Source
AI summary
A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.