Embedded Substrate Via Interconnects for Chip Terminal Layout
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Solution Overview
Problem
Existing electronic component built-in substrates require additional wiring routing below capacitor elements to connect power supply and ground lines from both surfaces, limiting semiconductor chip terminal layout design freedom and leading to potential voids in underfill resin due to convex wiring layers.
Innovation Solution
An electronic component built-in substrate with a novel structure where wiring paths are connected to electrodes from both surfaces of an insulating base material, using via conductors to connect the first and second wiring layers to the electrodes, eliminating the need for additional wiring routing and ensuring a flat surface for underfill resin filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an extra routing of wiring layer is formed below the capacitor element to connect power supply lines and ground lines from both surfaces, then the connectivity between wiring layers and capacitor electrodes is improved, but the layout freedom of semiconductor chip terminals is reduced and design freedom is lowered
Solution Approach 1:
The patent transitions from planar wiring routing to three-dimensional via hole connections. Instead of routing wiring layers horizontally below the capacitor element, the invention uses via holes to connect wiring layers vertically from both upper and lower surfaces of the substrate to the capacitor electrodes, eliminating the need for extra horizontal routing space and preserving design freedom.
Solution Approach 2:
The patent introduces via holes as intermediary connection structures between wiring layers and capacitor electrodes. These via holes act as mediators that enable direct vertical connections from both surfaces of the substrate to the capacitor electrodes, replacing the need for complex extra wiring layer routing and maintaining layout flexibility.
2Adaptability or versatility
If wiring paths are connected from both surfaces of the insulating base material using via conductors, then design freedom for semiconductor chip terminals is enhanced and underfill resin filling reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses vertical via hole connections from both surfaces of the substrate to achieve wiring connectivity, eliminating the need for complex extra wiring layer routing. This dimensional approach simplifies the overall structure and manufacturing process compared to traditional planar routing methods.
Data Source
AI summary
An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.