Embedded Substrate Via Structure for Void-Free Deep Connections
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Solution Overview
Problem
Existing electronic component embedded substrates with multilayer wiring structures face issues such as voids in deep via conductors and inferior adhesiveness between via conductors and shallow vias, leading to potential connection reliability problems, especially under high heat conditions.
Innovation Solution
The substrate design includes first and second insulating layers with an electronic component in between, featuring a first via conductor filling a deep via and a second via conductor filling a shallower via that overlaps the first, with the second via having increased surface roughness and a barrel-shaped lower section to enhance adhesion and prevent voids, while using resin materials without core materials to reduce void formation during electrolytic plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via conductor is formed in a deep via, then connection between conductor layers is achieved, but voids occur in the via conductor
Solution Approach 1:
The patent applies local quality by making the inner wall surface roughness different at different locations of the via. Specifically, the inner wall of the via has a rough surface (with peaks and valleys) in the lower section where voids tend to form, and a smoother surface in the upper section. This localized surface roughness variation prevents void formation at the bottom while maintaining good plating quality overall, thus resolving the contradiction between achieving deep via connection and preventing voids.
2Temperature
If the via diameter simply decreases in the depth direction, then heat dissipation is improved, but connection reliability at the bottom portion deteriorates due to heat
Solution Approach 1:
The patent divides the via into different sections with different diameters: an upper section with smaller diameter for heat dissipation, and a lower section with larger diameter for maintaining connection reliability. This local variation in via diameter allows the structure to simultaneously achieve both heat dissipation performance and reliable electrical connection at the bottom portion where heat accumulation is most severe.
Solution Approach 2:
The via has a curved, barrel-shaped profile rather than a simple tapered or cylindrical shape. The via diameter decreases gradually from the bottom to the top, creating a smooth curved transition. This curved geometry optimizes both heat dissipation (by reducing overall diameter in upper sections) and connection reliability (by maintaining adequate diameter at the bottom section).
3Manufacturing precision
If resin material is used without core material, then void formation during electrolytic plating is reduced, but embedding of electronic component may be hindered
Solution Approach 1:
The patent applies local quality by using different resin material compositions in different regions. The lower section of the via (where voids form during plating) is surrounded by resin without core material to prevent void formation. The upper section and surrounding areas use resin with core material to facilitate electronic component embedding and provide mechanical support. This spatial differentiation resolves the contradiction between void prevention and component embedding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents voids in deep via conductors and improves adhesiveness between via conductors and shallow vias, enhancing connection reliability at the bottom portion of the via conductor even under high heat conditions.
Implementation Method 1
making voids less likely to occur during formation of the first via conductor by electrolytic plating
Data Source
AI summary
An electronic component embedded substrate includes conductor layers L1 to L3, insulating layers 112 and 113 provided between the conductor layers L2 and L3, an insulating layer 114 provided between the conductor layers L1 and L2, a semiconductor embedded in the insulating layers 112 and 113, a via conductor 142 filling a via V, and a via conductor 143 filling a via 143a. The via 143a is provided at such a position that overlaps the via V and is shallower than the via V. The inner wall of the via 143a is larger in surface roughness than the inner wall of the via V. This makes voids less likely to occur in the via conductor 142 filling the deep via V and enhances adhesion between the via conductor 143 and the shallow via 143a that the via conductor 143 fills.