Embedded Substrate Via Design for Warpage Crack Reduction

Solution Overview

Problem

The miniaturization and slimming of electronic devices lead to warpage issues in substrates, causing cracks in connecting portions of electronic components and circuit patterns, which deteriorate the reliability and increase the failure rate of electronic devices due to differences in thermal expansion coefficients and surface roughness limitations.

Innovation Solution

An electronic component embedded substrate design featuring an insulating layer with a cavity, an electronic component with an external electrode, a conductor pattern, a build-up insulating layer, and vias with specific cross-sectional area and diameter ratios, where the first via has a larger contact portion than the second via, and the conductor pattern has increased surface roughness compared to the external electrode, to enhance contact stability and reduce warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the size of electronic components and via diameter are reduced to achieve miniaturization, then the slimming of electronic devices is improved, but the warpage-induced cracks in connecting portions occur more frequently

Engineering Contradiction:

Improvesize of electronic componentsVSAvoidreliability of connecting portions

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a roughness layer specifically at the contact portion of the via where it interfaces with the external electrode, while other portions of the via maintain smooth surfaces. This localized surface treatment enhances adhesion and stress distribution precisely where thermal expansion differences cause cracking, without affecting the overall miniaturization of the component.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the surface parameter (roughness) of the via contact portion to improve mechanical interlocking and adhesion strength. By controlling the roughness depth within a specific range (0.1-10 μm), the invention optimizes the balance between enhanced bonding strength and minimal impact on via structural integrity during thermal cycling.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the via cross-sectional area is reduced to achieve higher density, then the productivity and miniaturization are improved, but the cracks in via and circuit pattern occur more frequently due to warpage

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidstrength of connecting portions

Core Design Contradiction:

ProductivityVSStrength

Solution Approach 1:

The patent applies local quality by creating a roughness layer specifically at the contact portion of the via where it interfaces with the external electrode, while other portions of the via maintain smooth surfaces. This localized surface treatment enhances adhesion and stress distribution precisely where thermal expansion differences cause cracking, without affecting the overall miniaturization of the component.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent creates a composite structure at the via contact portion by forming a roughness layer that combines the via conductive material with the surrounding insulating material. This composite interface provides both mechanical interlocking and thermal stress relief, enhancing the overall strength of the connecting portion while maintaining small via dimensions.

Inventive Principle:

Principle #40Composite materials

3Length of stationary object

If the substrate thickness is reduced to achieve slimming, then the portability is improved, but the warpage causes cracks in contact region of external electrode and via

Engineering Contradiction:

Improvethickness of substrateVSAvoidreliability of contact region

Core Design Contradiction:

Length of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a roughness layer specifically at the contact portion of the via where it interfaces with the external electrode, while other portions of the via maintain smooth surfaces. This localized surface treatment enhances adhesion and stress distribution precisely where thermal expansion differences cause cracking, without affecting the overall miniaturization of the component.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements beforehand cushioning by pre-forming a roughness layer at the via contact portion before final assembly and thermal cycling. This pre-prepared rough surface structure acts as a cushioning mechanism that absorbs and distributes thermal stress during subsequent temperature variations, preventing crack initiation in the contact region.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9386702B2Electronic component embedded substrate and method of manufacturing electronic component embedded substrate

Publication Date: 2016.07.05 SAMSUNG ELECTRO MECHANICS CO LTD

AI summary

An electronic component embedded substrate and a method of manufacturing an electronic component embedded substrate, The substrate includes a first via passing through a part of an insulating portion of the substrate to an electrode of the electronic component, and a second via passing through a part of the insulating portion to the conductor pattern. The second via has a contact portion with a smaller cross-sectional area than the cross-sectional area of a contact portion of the first via.