Embedded Component Substrate Warpage and ESL Reduction
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Solution Overview
Problem
The challenge is to create an electronic component-embedded substrate that reduces warpage, enhances power integrity by increasing capacitance and decreasing equivalent series inductance, and shortens electrical connection paths while accommodating the increasing number of electronic components on miniaturized printed circuit boards.
Innovation Solution
The substrate design includes a first and second wiring layer with insulating materials covering electronic components, via structures connecting these layers, and a parallel electrical connection between components, which reduces warpage and improves power integrity by increasing capacitance and decreasing ESL, while maintaining a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electronic components are embedded in the substrate, then the electrical connection path is shortened and power integrity is improved, but the manufacturing complexity and warpage control become more difficult
Solution Approach 1:
The patent transitions from traditional surface-mounted electronic components to embedded components within the substrate layers. This dimensional change allows components to be integrated inside the substrate rather than mounted on the surface, shortening electrical connection paths and improving power integrity while maintaining a compact form factor.
Solution Approach 2:
The patent implements a multi-layer nested structure where electronic components are embedded within insulating material layers, which are themselves nested between wiring layers. The first electronic component is embedded in the first insulating material, and the second electronic component is embedded in the second insulating material, creating a compact nested arrangement that reduces overall device size and improves electrical connectivity.
2Length of moving object
If electronic components are embedded in the substrate, then the electrical connection path is shortened, but warpage of the substrate increases
Solution Approach 1:
The patent employs asymmetric design in the wiring layers, where the first wiring layer and second wiring layer are positioned at different heights and configurations relative to the embedded components. This asymmetric wiring arrangement helps balance the mechanical stresses and thermal expansions within the substrate, thereby reducing warpage while maintaining short electrical connection paths.
Solution Approach 2:
The patent modifies physical parameters such as the thickness of insulating materials, the positioning of wiring layers, and the configuration of via holes to optimize both the electrical connection path length and the mechanical stability of the substrate. By carefully adjusting these parameters, the patent achieves short electrical paths while minimizing warpage through balanced stress distribution.
3Reliability
If the number of electronic components is increased to maintain functionality, then the capacitance and power integrity improve, but the area occupied on the substrate increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple wiring layers and embedded components to increase capacitance and functionality without expanding the horizontal substrate area. By arranging electronic components and wiring in three-dimensional space with multiple layers stacked vertically, the patent achieves higher component density and improved power integrity within a compact footprint.
Solution Approach 2:
The patent embeds multiple electronic components within nested insulating material layers, allowing components to be positioned in three-dimensional space rather than spread out on the surface. This nested arrangement enables increased capacitance and component count while maintaining a small substrate area, as components are stacked and integrated within the substrate volume.
Data Source
AI summary
An electronic component-embedded substrate includes a first wiring layer, a first electronic component disposed on the first wiring layer, a first insulating material covering at least a portion of each of the first wiring layer and the first electronic component, a second wiring layer disposed on the first insulating material, a second electronic component disposed on the second wiring layer and connected to the first electronic component in an electrical parallel connection, a second insulating material disposed on the first insulating material and covering at least a portion of each of the second wiring layer and the second electronic component, and a first via penetrating through the first insulating material and connecting the first electronic component and the second wiring layer.