Embedded Substrate Multilayer Wiring Yield
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Solution Overview
Problem
The challenge lies in achieving high production yields and reliable electrical connections for semiconductor chips in multilayered wiring structures, as existing methods lead to lower efficiency and increased waste due to the complexity and miniaturization of chip embedded substrates.
Innovation Solution
A method involving the stacking of substrates with pre-formed wirings, where a semiconductor chip is encapsulated between two substrates, enabling electrical connection through an encapsulating connection layer, thereby forming reliable multilayered wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the wiring structure is miniaturized and multilayered to achieve high density mounting and downsizing, then the substrate footprint is reduced and mounting density is improved, but production time increases and production yields decrease
Solution Approach 1:
The substrate is divided into multiple layers with wirings distributed across different levels. This segmentation allows parallel processing of wiring formation on each layer, reducing overall production time while achieving high density mounting through vertical stacking of wiring layers.
Solution Approach 2:
The wiring structure transitions from two-dimensional planar arrangement to three-dimensional multilayer configuration. By adding the vertical dimension with multiple wiring layers, the substrate achieves higher mounting density without increasing footprint, while standardized layer stacking processes improve production efficiency.
2Area of moving object
If the wiring structure is miniaturized and multilayered to achieve high density mounting, then the substrate footprint is reduced, but production yields decrease due to increased complexity
Solution Approach 1:
The complex wiring structure is segmented into multiple standardized layers, each with defined functions and connection patterns. This modular segmentation simplifies the manufacturing process for each layer while achieving overall high density, thereby improving production yields despite the multilayered configuration.
Solution Approach 2:
Standardized parameters are established for wiring layer thickness, spacing, and material properties. By controlling these parameters across all layers, the complexity of miniaturized multilayered wiring is managed systematically, ensuring consistent quality and high production yields.
3Quantity of substance
If expensive semiconductor chips are embedded in the substrate with miniaturized multilayered wiring, then high density mounting is achieved, but lower production yields lead to waste of expensive chips
Solution Approach 1:
Wiring structures and connection patterns are pre-formed on substrate layers before semiconductor chip mounting. This preliminary preparation allows for pre-validation of wiring integrity and connection accuracy, enabling early detection of defects before expensive chips are attached, thereby reducing chip waste while achieving high mounting density.
4Area of moving object
If complex multilayered wiring structures are produced with extended production time, then high density mounting is achieved, but production efficiency decreases
Solution Approach 1:
The wiring formation process is segmented into independent layer-specific operations that can be performed in parallel. Each wiring layer is processed separately with standardized procedures, allowing simultaneous fabrication of multiple layers and reducing total production time despite the multilayered complexity.
Data Source
AI summary
An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.