Embedded Switches in Memory Arrays to Reduce Capacitive Loading
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Solution Overview
Problem
Existing memory devices face challenges with high bit line and select line capacitance, which affect operating speed and power consumption, particularly in three-dimensional memory arrays.
Innovation Solution
Incorporation of switches to selectively couple or decouple local lines to global lines in memory systems, reducing capacitive loading by configuring subsets of memory cells for access, thereby optimizing global line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays are used to increase storage density, then memory capacity is improved, but bit line and select line capacitance increases causing slower operating speed and higher power consumption
Solution Approach 1:
The memory array is divided into multiple blocks, with each block having its own dedicated bit lines and select lines. This segmentation isolates the capacitive loading to smaller subsets of memory cells, reducing the total capacitance that each driver must handle and thereby improving operating speed while maintaining high overall capacity through the combined blocks.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory arrays to three-dimensional stacked memory structures. By stacking multiple memory layers vertically, the design achieves higher storage density without proportionally increasing the bit line and select line capacitance, as the same line structures serve multiple layers through the stacking architecture.
2Quantity of substance
If three-dimensional memory arrays are used to increase storage density, then memory capacity is improved, but power consumption increases due to higher capacitive loading
Solution Approach 1:
By segmenting the memory array into multiple blocks with dedicated bit lines and select lines for each block, the capacitive loading on each line is reduced. This segmentation allows drivers to charge and discharge smaller capacitances during read/write operations, directly reducing the energy consumed per operation while the overall memory capacity remains high due to the combined blocks.
Solution Approach 2:
The patent implements dynamic control of bit lines and select lines through block selection mechanisms. Only the blocks that are currently being accessed have their bit lines and select lines activated, while other blocks remain in a high-impedance state. This dynamic activation reduces the total capacitive loading that must be driven at any given time, thereby reducing power consumption while maintaining high memory capacity.
Data Source
AI summary
One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.