Embedded Artificial Synaptic Element With Complementary Memristors
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Solution Overview
Problem
Current neural network systems face challenges in constructing and training synaptic elements due to the lack of detailed silicon data representation, leading to inconsistencies in accuracy and compatibility issues with Complementary Metal-Oxide-Semiconductor (CMOS) logic circuits, and existing memristor-based solutions struggle with high-power consumption and low transmission efficiency.
Innovation Solution
A high-density embedded-artificial synaptic element is developed, comprising a semiconductor substrate, select transistor, and memory transistor with complementary memristors, utilizing a metal layer to connect the drain region of the select transistor to the memory transistor's gate structure, allowing for operation in high and low resistive states to form a Non-Volatile Memory Latch, enabling efficient data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memristors are used for data storage in neural network systems, then power consumption is reduced and durability is improved, but logic gate compatibility with CMOS circuits is lost
Solution Approach 1:
The patent combines memristor-based synaptic elements with CMOS transistor logic gates into a unified hybrid structure. The memristor provides non-volatile storage and neural network functionality, while the CMOS transistor layer restores logic gate compatibility, allowing the system to benefit from both low-power memristor characteristics and standard CMOS circuit integration.
2Extent of automation
If synaptic elements are constructed based on mathematical models, then machine learning training is enabled, but detailed silicon data representation is lost leading to accuracy inconsistencies
Solution Approach 1:
The patent introduces a hybrid memristor-transistor structure that acts as an intermediary between mathematical models and physical silicon implementation. The transistor layer provides precise control and readout mechanisms that bridge the gap between abstract training algorithms and concrete hardware behavior, ensuring consistent accuracy across different operating conditions and manufacturing variations.
3Reliability
If traditional computing units are used, then logic operations are performed, but reliability issues arise due to high power consumption and low transmission efficiency
Solution Approach 1:
The patent replaces traditional von Neumann architecture with a Computing-in-Memory architecture where memristors perform both storage and computation functions. This substitution eliminates the need for data movement between separate memory and processing units, dramatically reducing power consumption and improving reliability by keeping computation close to where data is stored.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable and efficient data output, achieving higher data density and reducing power consumption, while maintaining a robust read window despite manufacturing variations, enhancing the performance of neural network systems and Computing In Memory (CIM) applications.
Implementation Method 1
The first memristor and the second memristor are set in response to a write voltage to a low resistive state and a high resistive state, respectively, or are set in response to the write voltage to a high resistive state and a low resistive state, respectively
Data Source
AI summary
A high density embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region.