Embedded System SEU Protection via Parity and ECC
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Solution Overview
Problem
Embedded systems with integrated circuit memories are susceptible to single event upset (SEU) effects due to energetic particle strikes, and existing solutions either increase complexity or cost, such as adding capacitance or resistance to memory cells, which is undesirable.
Innovation Solution
The use of a combination of parity checking in the instruction memory and error correction coding in the data memory, with a controller that replaces instruction sets in the instruction memory with copies from non-volatile memory upon error detection, reduces susceptibility to SEU effects in a cost-efficient manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitance or resistance is added to memory cells to reduce SEU susceptibility, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent implements a copying principle by maintaining a backup copy of the instruction set in non-volatile memory. When a parity error is detected in the instruction memory, the controller automatically replaces the corrupted instructions with the backup copy from non-volatile memory, thereby protecting against SEU effects without modifying the memory cell structure.
Solution Approach 2:
The patent extracts the error protection function from the memory cell itself and implements it at the system level through parity checking and backup copying mechanisms. This separates the storage function (memory cells) from the protection function (parity bits and backup copy), avoiding the need to add complexity within individual cells.
2Reliability
If capacitance is increased to decrease SEU susceptibility, then reliability improves, but write time increases
Solution Approach 1:
The patent uses a copying mechanism where a backup copy of the instruction set is maintained in non-volatile memory. This allows the system to protect against SEU effects without increasing the capacitance of memory cells, thereby maintaining fast write times while improving reliability.
3Reliability
If additional capacitance and resistance are added to storage nodes, then SEU susceptibility decreases, but integrated circuit surface area increases
Solution Approach 1:
The patent implements protection against SEU effects through a copying mechanism that maintains a backup copy of instructions in non-volatile memory, rather than adding capacitance and resistance to storage nodes. This approach protects reliability without increasing the surface area of individual memory cells.
Solution Approach 2:
The patent extracts the error protection mechanism from the physical memory cell structure and implements it through logical means (parity checking and backup copying), thereby avoiding the need to increase the surface area of storage nodes while maintaining SEU susceptibility protection.
Data Source
AI summary
An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a non-volatile memory that can store a copy of the at least one instruction set, and a data memory that can store at least one data sequence. The data memory utilizes an error correction coding (ECC) scheme. A controller, which is responsive to the instruction memory, the non-volatile memory, and the data memory, replaces the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory, if a parity error is detected in connection with the at least one instruction set in the instruction memory. The controller also operates in conjunction with the data memory to implement the ECC scheme.