Embedded Touch Display Parasitic Capacitance Minimization
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Solution Overview
Problem
In-cell embedded touch display devices with liquid crystal structures in IPS or FFS modes suffer from inaccurate touch determination due to changes in parasitic capacitance caused by the inversion of liquid crystal molecules.
Innovation Solution
The solution involves a capacitive touch display device structure with a specific distance range (4 μm to 7 μm) between the touch electrode and the liquid crystal layer, utilizing a planarization layer and dielectric layers to minimize the impact of parasitic capacitance, and includes a capacitive touch structure with parallel sensing and drive electrodes connected through via holes, and a protective metal layer to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the touch electrode is placed close to the liquid crystal layer to reduce device thickness, then the device thickness is reduced, but parasitic capacitance increases causing inaccurate touch determination
Solution Approach 1:
The patent introduces a planarization layer as an intermediary between the touch electrode and the liquid crystal layer. This planarization layer provides electrical isolation that reduces parasitic capacitance while still allowing the touch electrode to be positioned close to the liquid crystal layer, thus maintaining both thin profile and accurate touch determination.
2Measurement precision
If the distance between touch electrode and liquid crystal layer is increased to reduce parasitic capacitance, then touch determination accuracy improves, but device thickness increases
Solution Approach 1:
The planarization layer serves as a mediator that enables the touch electrode to maintain optimal distance for reduced parasitic capacitance without significantly increasing overall device thickness, as the planarization layer itself is a thin functional layer.
Solution Approach 2:
The patent optimizes the distance parameter between the touch electrode and liquid crystal layer to a specific range (4-7 μm) that balances parasitic capacitance reduction with device thickness constraints, achieving both accurate touch determination and thin profile.
3Length of stationary object
If in-cell embedded touch technology is used to integrate touch panel and liquid crystal panel, then device thickness and weight are reduced, but parasitic capacitance interference increases
Solution Approach 1:
The planarization layer acts as an intermediary that provides electrical isolation between the touch electrode and liquid crystal components, reducing parasitic capacitance interference while maintaining the integrated in-cell structure's thickness advantages.
Solution Approach 2:
The patent applies local quality by introducing the planarization layer specifically at the interface between touch and display components where parasitic capacitance is generated, providing targeted electrical isolation without affecting other parts of the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the interference from parasitic capacitance changes, improving the accuracy of touch determination in the embedded touch display device.
Implementation Method 1
a distance between the touch electrode and the liquid crystal layer is in a range of 4 μm to 7 μm
Data Source
AI summary
An embedded touch control display device is disclosed. The embedded touch control display device includes a first substrate and a second substrate which are set oppositely; an in-plane switching (IPS) or fringe field switching (FFS) display mode display structure and a capacitance touch structure which are set between the first substrate and the second substrate, and the IPS or FFS display mode display structure is located on the first substrate and comprises a pixel electrode layer, a first medium layer, a public electrode layer and a crystal layer, and the capacitance touch structure is located on the second substrate and comprises touch electrode and a second medium layer; an planarization layer which is located between the second medium layer and the crystal layer; the distance between the touch electrode and the crystal layer is 4 micrometers to 7 micrometers.