Double-Sided Embedded Trace Substrate for Fine-Pitch Packaging
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Solution Overview
Problem
The challenge lies in creating a substrate that allows for smaller form factors and finer pitches in integrated circuits and electronic devices while reducing the need for separate packaging, which is costly and space-consuming.
Innovation Solution
A double-sided embedded trace substrate is developed, comprising two portions with metal layers separated by insulating layers, connected through posts and interconnects, allowing direct electrical coupling of surface mount circuit components without separate packaging, and utilizing solder interconnects or posts for bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If separate package substrates are used for surface mount devices, then electrical coupling is achieved, but overall device height and cost increase
Solution Approach 1:
The patent merges the package substrate functionality directly into the electronic device substrate. The substrate includes first and second portions with metal layers and insulating layers that provide both device functionality and package substrate electrical coupling capabilities. This integration eliminates the need for separate package substrates, reducing overall device height and simplifying the packaging structure while maintaining electrical coupling functionality.
2Productivity
If finer pitches are used in electrical routing boards, then input/output increases, but manufacturing precision requirements increase
Solution Approach 1:
The substrate is segmented into first and second portions, each with their own metal layers and insulating layers. This segmentation allows independent optimization of each portion for finer pitches and higher I/O density without compromising overall manufacturing precision. The first portion can be optimized for specific routing requirements while the second portion handles other connections, enabling finer pitches to be achieved more readily.
3Area of moving object
If smaller form factors are used in integrated circuits, then device size decreases, but space for electrical routing is reduced
Solution Approach 1:
The patent utilizes multiple layers (first and second metal layers in each portion, separated by insulating layers) to provide three-dimensional routing paths. This dimensional approach allows electrical routing to occur in multiple planes, effectively increasing the routing capacity within a reduced two-dimensional footprint. The vertical stacking of metal layers and insulating layers enables complex routing patterns to be achieved in a compact form factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the overall height and cost of packaging, enabling smaller, more efficient electronic devices with finer pitches and eliminating the need for separate package substrates, thereby saving space and resources.
Implementation Method 1
The plurality of interconnects comprise a plurality of solder interconnects. The method comprises coupling the first plurality of posts to the plurality of solder interconnects, and coupling the first portion of the substrate to the second portion of the substrate
Data Source
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AI summary
Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.