Embedded Trace Package Substrate with Raised Pillars for Fine-Pitch Joints
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges with reduced line-spacing ratio (L/S) interconnects in embedded trace substrates (ETS) that are easily consumed by solder, leading to potential cracking and interconnection failure, especially in high-density die applications.
Innovation Solution
Incorporation of raised metal pillar interconnects in the ETS layer, which are formed above the surface of the ETS layer to increase volume and reduce metal consumption, allowing for smaller L/S interconnects without cracking, and providing enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reduced line-spacing ratio (L/S) interconnects are used in the ETS layer to increase connection density, then the number of interconnects per unit area increases, but the interconnects become more susceptible to metal consumption by solder
Solution Approach 1:
The patent transitions from planar 2D interconnect traces to 3D vertical metal pillar structures. The ETS layer contains horizontal traces that connect to vertically extending metal pillars, creating a three-dimensional interconnect architecture. This dimensional change allows the interconnect volume to increase without expanding the footprint, thereby maintaining high connection density while providing sufficient metal volume to prevent consumption by solder during die attachment.
2Productivity
If smaller L/S interconnects are used to support high-density dies, then more interconnects can be accommodated, but the risk of ETS layer cracking increases due to metal consumption
Solution Approach 1:
The patent creates a composite interconnect structure combining horizontal ETS traces embedded in dielectric material with vertical metal pillars. The ETS layer comprises a dielectric matrix with embedded metal traces, which are then coupled to raised metal pillars formed through the dielectric surface. This composite architecture provides both the high density of the ETS traces and the structural strength of the volumetric metal pillars, preventing cracking while maintaining high interconnect density.
3Reliability
If metal pillar interconnects are raised above the ETS layer surface to increase volume, then metal consumption is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the interconnect formation into distinct fabrication stages: first forming the ETS traces in the dielectric layer, then creating openings through the dielectric surface, and finally depositing metal to form vertical pillars. This segmentation allows each step to be optimized independently using standard semiconductor manufacturing techniques, managing process complexity while achieving the volumetric metal structures needed to prevent consumption.
Data Source
AI summary
Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (μm)/5.0 μm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.