Embedded Conductive Trace Base for Dense Flip-Chip Packaging
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Solution Overview
Problem
High-density flip-chip semiconductor packages face thermal electrical problems such as heat dissipation, cross talk, signal propagation delay, and electromagnetic interference due to increased input/output connections, which affect the reliability and quality of products.
Innovation Solution
The semiconductor package incorporates conductive traces embedded in a base, with top surfaces recessed below the device attach surface, preventing bump-to-trace bridging and enhancing routing ability for high-density packages. The conductive traces are designed with widths larger than 5µm, and the base can be a single or multilayer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of input/output connections is increased to achieve high-density packaging, then the packaging density and functionality are improved, but thermal electrical problems such as heat dissipation, cross talk, signal propagation delay, and electromagnetic interference worsen
Solution Approach 1:
The patent transitions from planar trace routing to three-dimensional vertical trace routing by forming conductive traces that extend through the thickness of the substrate. This vertical dimension allows traces to be positioned deeper within the substrate structure, increasing the distance between adjacent traces and reducing electromagnetic interference and cross-talk while maintaining high I/O connectivity
Solution Approach 2:
The patent embeds conductive traces within the substrate structure, nesting them between different layers of the package. The traces are positioned within recesses or cavities in the substrate, allowing multiple routing layers to be stacked vertically. This nesting approach enables high-density interconnection while spatially separating traces to minimize thermal and electrical interference
2Productivity
If line widths are minimized to increase the number of connections, then the packaging density is improved, but manufacturing precision and reliability worsen due to smaller feature sizes
Solution Approach 1:
The patent changes the routing geometry from horizontal to vertical, forming traces that extend through the substrate thickness rather than across its surface. This dimensional change allows for larger effective trace cross-sections and greater spacing between adjacent traces, improving manufacturability and reliability while achieving high connection density through the vertical stacking of multiple routing layers
Solution Approach 2:
The patent divides the interconnection structure into multiple discrete vertical trace segments distributed throughout the substrate thickness. Each vertical trace can be independently formed and controlled, allowing for better manufacturing precision. The segmentation also enables independent optimization of each trace layer without affecting adjacent traces, improving overall reliability
Data Source
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AI summary
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.