Embedded Traces Fabrication via Reusable Carrier and 3D Conformal Plating
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Solution Overview
Problem
The high cost of substrate fabrication using disposable carriers and the increasing need for more interconnects on substrates in microelectronic packaging pose challenges in achieving efficient and cost-effective mechanical support and electrical connectivity for electronic components.
Innovation Solution
The method involves forming embedded traces and metal-filled vias using photolithography and plating, where traces extend along the surface and sidewalls of bumps, providing mechanical support and electrical connectivity, and cross-directional traces are formed to enhance attachment and reduce shifting during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If disposable carriers are used for substrate fabrication, then the fabrication process is simple and fast, but the fabrication cost is high
Solution Approach 1:
The patent recovers and reuses the carrier substrate after removing the fabricated interconnect structure. The carrier is cleaned and prepared for subsequent fabrication cycles, transforming a disposable single-use approach into a reusable system that reduces material waste and fabrication costs while maintaining high productivity
Solution Approach 2:
The patent changes the physical and chemical parameters of the carrier surface through coating and treatment processes, enabling the carrier to be reused multiple times. The surface properties are modified to allow repeated deposition and etching cycles without degradation, thus reducing per-unit fabrication cost while maintaining production speed
2Reliability
If the number of interconnects on substrates is increased, then electrical connectivity is improved, but the substrate complexity increases
Solution Approach 1:
The patent segments the interconnect formation process into multiple sequential steps: depositing conductive material, forming dielectric layers, creating vias, and patternning traces. This segmentation allows complex multi-layer interconnect structures to be built systematically, improving electrical connectivity while managing substrate complexity through controlled process steps
Solution Approach 2:
The patent transitions from two-dimensional planar interconnects to three-dimensional multi-layer structures with vertical vias and stacked conductive layers. This dimensional expansion enables significantly increased interconnect density and electrical connectivity capacity while organizing complexity into structured vertical layers rather than chaotic planar arrangements
3Strength
If embedded traces are formed over bumps, then mechanical support and electrical connectivity are provided, but the fabrication process complexity increases
Solution Approach 1:
The patent merges the trace formation process with the existing bump structure by depositing conductive material that conforms to the bump topography. The trace is integrated with the bump in a single continuous deposition and etching process, providing mechanical support and electrical connectivity simultaneously without requiring separate fabrication steps, thus managing process complexity while achieving dual functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and increases the number of interconnects on substrates, providing robust mechanical support and reliable electrical connections for electronic components while maintaining attachment stability.
Implementation Method 1
The trace is formed using photolithography and plating
Implementation Method 2
The trace is formed using photolithography and plating
Data Source
AI summary
Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.