Embedded Via Structure With Hard Film Layer Against Cracking
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Solution Overview
Problem
Current methods for creating conductive via structures in multi-chip packages face challenges such as limited scalability and accuracy due to UV laser drilling, and lithographically defined vias are prone to mechanical and electrical reliability issues due to thermal expansion mismatches.
Innovation Solution
The implementation of a via structure with a thin film layer of high hardness as an adhesion layer and crack barrier, which covers conductive features in the MCP substrate, enabling finer pitch architectures and better alignment while mitigating stress fractures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If UV laser drilling is used to create via structures, then via structures can be created in MCP substrate, but manufacturing precision and scalability are limited due to inherent wavelength limitations and taper effects
Solution Approach 1:
The patent replaces the mechanical UV laser drilling process with a chemical etching process using inductively coupled plasma (ICP). This substitution eliminates the wavelength limitations and taper effects inherent in laser drilling, enabling precise control of via aperture sizes down to 10 microns or less with vertical sidewalls and improved manufacturing scalability.
Solution Approach 2:
The patent changes the fundamental process parameters by transitioning from thermal laser ablation to chemical plasma etching. This parameter change enables new levels of precision in via aperture control and eliminates the taper angle problem, achieving vertical sidewalls and apertures at the 10-micron scale that were not achievable with UV laser drilling.
2Manufacturing precision
If lithographically defined vias are used to achieve smaller pitches, then manufacturing precision improves, but mechanical and electrical reliability deteriorates due to thermal expansion mismatches causing stress fractures
Solution Approach 1:
The patent employs a composite via structure consisting of a copper fill material within the via aperture, surrounded by a dielectric material, and lined with a barrier metal layer. This composite structure accommodates thermal expansion mismatches between different materials, preventing stress fractures while maintaining the small pitch dimensions achieved through ICP etching.
Solution Approach 2:
The patent incorporates a barrier metal layer and carefully selected dielectric materials with appropriate thermal expansion coefficients to cushion against thermal stress before it can cause fractures. This preventive approach addresses thermal expansion mismatches before they lead to reliability failures during thermal cycling.
3Measurement precision
If via aperture size is reduced to achieve finer pitch architectures, then alignment precision improves, but manufacturing difficulty increases due to process control challenges at smaller dimensions
Solution Approach 1:
The patent replaces mechanical contact-based alignment methods with optical alignment techniques enabled by the ICP etching process. This substitution allows for precise alignment at 10-micron aperture sizes and below, with the added benefit that the chemical process is more inherently controllable than mechanical drilling at such small dimensions.
Solution Approach 2:
The patent uses lithographic patterning to create precise masks that define via locations and dimensions before ICP etching. This copying approach from the lithographic pattern to the final via structure enables high alignment precision while simplifying process control, as the lithography step establishes the geometric template for subsequent self-aligned processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for smaller pitches and more precise alignment of conductive vias, enhancing mechanical and electrical reliability by preventing crack propagation and improving thermal expansion mismatch issues.
Implementation Method 1
coating the conductive features with a thin film layer of a high hardness to function as an adhesion layer
Implementation Method 2
coating the conductive features with a thin film layer of a high hardness to function as an adhesion layer and a barrier to crack propagation
Implementation Method 3
lithographically defined conductive vias (LIV) or pillars have been presented. The LIV approach deposits a conductive pillar and thereby enables smaller bump pitch scaling and better alignment than the UV laser approach. However, with the LIV approach, adjacent materials with mismatched coefficients of thermal expansion (CTE) can be vulnerable to stress.
Data Source
AI summary
A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface. The film layer can act as a barrier to cracking because it is selected to have a higher hardness than the material making up the dielectric layer